But yeah I'd be willing to support that use case

Hi all! Who is the author for yosys?

Claire Wolf. She's not part of this Slack.

Hi everyone, I am fishing for expert tips if OpenLane is struggling in the detailed router phase. I think the design is not space constrained (utilization set to 20%). Any useful parameter settings that I could try, or things to watch for in the log files?

Any macros? I had issue where drt would struggle if macro's pins where on horizontal metals while the pins themselves being vertical

1) How do I verify, that the power supply for the SRAMs is correct \ sufficient ? Is there a checklist ?

2) Should I try making it more compact (the only argument is to make it look more sexy) or should I extend the macro to the fullest (now it is 2600x2600) and try to place the SRAMs close to the chip boundaries, since it is not really timing critically (though dream frequency is 150MHz). Or should I leave it as it is ?

1. No easy way, porbably parasitic extraction and simulation with timings could verify this, but it's actually super hard/long. I would go 0.1V IR drop, so around 2ohm resistance. Check if parasitics gets you that or if you get more, make wires more wide. Dont forget, low voltages create only one issue: Timings might not be good. 2. You are the only person that can answer that, because we dont know what are you trying to achieve. Sometimes optimal == matching requirements and overenignnering is not worth the time.

reposting here in case you know the answer, this is for openroad

For second redirect cmd from tcl should be enough.

@User @User noticed that the open_pdks version requirements for

magic

seems to be different from the one shipped in

efabless/openlane:latest

/open_pdks/sky130/sky130A/libs.tech/magic/sky130A.tech: line 19: section version:
	Error:  Magic version 8.3.260 is required by this techfile, but this version of magic is 8.3.209.

This may be a question for #openroad, but it seems that unused io signals are synthesized as connections to ground. For example, in this rtl, the output signals

io_out

are unused. In the resulting gate level verilog, these signals have all been tied to ground.

sky130_fd_sc_hd__conb_1 _60713_ (.LO(io_out[0]),
    .VGND(vssd1),
    .VNB(vssd1),
    .VPB(vccd1),
    .VPWR(vccd1));

This can lead to unexpected results, if "unused" signals are shared with actual signals from other modules. Is this a yosys issue? @User

Does anyone have experience with the pdn controls that look like this?

pdngen::specify_grid_macro {
		power_pins "VDD"
		ground_pins "GND"
		blockages "li metal1 metal2"
		connect {{metal1_PIN metal2} {metal2 metal3} {metal3 metal4} {metal4 metal5}}
	}

I have a black_box macro with pins VDD and GND. I'm having trouble getting this to connect to the power rails

Untitled.txt

Anybody else has issue where OpenLane fast route segfaults? This only happens if I specify the def template. How am I supposed to use my own I/O placement, if it crashes when i specify def template. Same for CUGR

[  11.059] After normalization by unitWireCostRaw: 

[  11.059] unitWireCost (in DBU) = 1

[  11.059] unitViaCost (in DBU) = 2720

[  11.059] unitShortVioCost (coeff for "normal" short) = [500, 411.765, 411.765, 882.353, 882.353, 4705.88]

[  11.059] 

[  11.059] Init NetList ...

[ERROR]: during executing: "cugr -lef /openlane/designs/carrack_wrapper_user/runs/RUN_2022.02.08_13.41.21/tmp/merged_unpadded.lef -def /openlane/designs/carrack_wrapper_user/runs/RUN_2022.02.08_13.41.21/tmp/routing/17-addspacers.def -output /openlane/designs/carrack_wrapper_user/runs/RUN_2022.02.08_13.41.21/tmp/routing/18-fastroute.guide -threads 2 |& tee >&@stdout /openlane/designs/carrack_wrapper_user/runs/RUN_2022.02.08_13.41.21/logs/routing/18-fastroute.log"

Somehow magic works in OpenLane docker, but klayout not

Screenshot from 2022-02-10 15-14-26.png

what is the problem with this?

Did anybody successfully used OpenRoad generated DEFs in OpenLane run? OpenLane's generated defs used as template works fine, but not the one that is generated by OpenRoad script I found a weird bug for using DEFs in OpenLane. https://github.com/The-OpenROAD-Project/OpenLane/issues/912

Can we use SystemVerilog for design? Looks like yosys do support, is it enough for efabless submission?

If it works in the flow then its fine

Yosys supports a limited subset of sv

Thank you Matt, I will give it a try

@User it's also possible to get support using surelog + the uhdm plugin, https://github.com/SymbiFlow/yosys-symbiflow-plugins#uhdm-plugin

the good folks from antmicro wrote a blog post about it earlier last year: https://antmicro.com/blog/2021/10/openlane-asic-build-flow-with-systemverilog-support/

STA in Openlane doesn't appear to incorporate any macro timing information. How are we guaranteeing a design with macros makes timing? Also wondering if OpenROAD supports loading multiple SPEF files.

I notice a number of these in an openlane run where I'm integrating macros:

[WARNING ODB-0177] error: undefined via (via3_1600x480) referenced

It looks like it's caused by different settings for

FP_PDN_VWIDTH

and

FP_PDN_HWIDTH

in the macro and top level configs. I'll recreate my macros with the same PDN settings, but I was wondering how bad it is and if openlane should error out. I do see met4-met5 vias inside the macros in the final GDS.

hello! just checking in, is there an easy way to disable CTS yet?

This is the current latest yosys tag openlane is using? https://github.com/The-OpenROAD-Project/OpenLane/blob/master/dependencies/tool_metadata.yml#L71-L78