could we turn off the github connection on this channel? Or create a new openlane channel to have discussion?

How does OpenLane read the Value of pitch, it seems incorrect. Pitch should have been the center to center distance of 2 adjacent metal lines. However Openlane is skipping 1 metal line in PDN for pitch. It is taking the value as center to center distance between power/ground metal lines. @User Any idea? I have attached the snippets

#789 OpenLane flow get stuck at yosys part "Continuing TECHMAP pass" New issue created by ufukyill Hi I was trying to run my verilog code which is about 2k rows through OpenLane in order to get a gds file. (Im using ubuntu 18.04 via virtualBox.) When i run the command : "/.flow.tcl -design top_level" the flow stucks at ,exact same step, "Continuing TECHMAP pass" on every try and the virtual machine does not responds in anyway. Screenshot of log file is attached below. (I was able to get a gds file when i ran flow for some modules seperately. Then i put together these modules in a .v file which is compiled and tested). The-OpenROAD-Project/OpenLane

#789 OpenLane flow get stuck at yosys part "Continuing TECHMAP pass" Issue closed by donn The-OpenROAD-Project/OpenLane

#669 Update Yosys Issue closed by donn The-OpenROAD-Project/OpenLane

#779 Skipping few steps Issue closed by donn The-OpenROAD-Project/OpenLane

#785 Unable to run "make pdk" Issue closed by donn The-OpenROAD-Project/OpenLane

Unsubscribed from The-OpenROAD-Project/OpenLane

/github unsubscribe The-OpenROAD-Project/OpenLane

@User Done. Although I would prefer people use GitHub discussions anyway. More traceable.

back after some time since I want to update me and Olofs likely broken mpw2 submission for mpw4, unfortunately getting stuck immediately setting up the tools again.

klasn@klasn-jobb:~/mpw4/OpenLane$ make pull-openlane
Pulling most recent OpenLane image relative to your commit...
docker pull efabless/openlane:mpw-4
Error response from daemon: manifest for efabless/openlane:mpw-4 not found: manifest unknown: manifest unknown
make: *** [Makefile:191: pull-openlane] Error 1

Anybody recognize this issue?

[INFO]: Back-up GDS-II streamed out.
[INFO]: Incremented step index to 29.
[INFO]: Running XOR on the layouts using Klayout...
First Layout: /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/results/finishing/spm.gds
Second Layout: /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/results/finishing/spm.klayout.gds
Design Name: spm
Output GDS will be: /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/reports/finishing/spm.xor.gds
ERROR: Unable to determine format for file from suffix or format spec /mnt/sky130/mpw4/openlane_workspace/openlane/scripts/klayout/xor.drc
[ERROR]: during executing: "bash /mnt/sky130/mpw4/openlane_workspace/openlane/scripts/klayout/xor.sh /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/results/finishing/spm.gds /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/results/finishing/spm.klayout.gds spm /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/reports/finishing/spm.xor.gds |& tee >&@stdout /mnt/sky130/mpw4/openlane_workspace/openlane/designs/spm/runs/RUN_2021.12.23_11.31.24/logs/finishing/30-xor.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

Does that ring a bell to anyone ?

Hey kiddos, trying to set up an openlane environment fro mpw4. Is it the efabless or openroad repo I should use? The efabless fork has an mpw-4 tag but all docs seems to say that the openroad version is the one to use

Ok, I'm assuming it's the mpw-4 tag. Will create a combined openlane+pdk image for this (like I did for version 0.12 here https://hub.docker.com/r/edalize/openlane-sky130) so that no one else needs to mess with building their own pdk and worry about whether they match the openlane version

Alright then. There's now a new openlane+sky130 image for the mpw4 tag available here https://hub.docker.com/r/edalize/openlane-sky130/tags You can use this to avoid having to build the pdk locally and have tools+pdk that are in sync. Can also be used together with FuseSoC to run openlane as a github CI action for any of your designs

Hi everyone, when I use

make full-pdk

to install the entire SKY130 PDK, I get a successful install of the

sky130_fd_sc_hd

library, but attempting to use other SCLs like

sky130_fd_sc_hs

results in groute not finding any diodes. Since my OpenLane install is 8 days old, I've `git pull`ed and will

make full-pdk

again, but I don't see anything in the commit log that looks like it would affect this.

@User Haven't dug very deep in the PDK. Does this mean

make pdk

only build a subset of the PDK?

So, I'm getting a bunch of slew rate warnings from the finished build, like

Pin                                    Limit    Slew   Slack
------------------------------------------------------------
_20535_/A                               1.50    2.21   -0.71 (VIOLATED)
_20164_/A                               1.50    2.21   -0.71 (VIOLATED)
_20901_/A                               1.50    2.21   -0.71 (VIOLATED)
_21281_/A                               1.50    2.20   -0.70 (VIOLATED)
_23513_/A                               1.50    2.20   -0.70 (VIOLATED)
_23143_/A                               1.50    2.20   -0.70 (VIOLATED)
_21649_/A                               1.50    2.20   -0.70 (VIOLATED)
ANTENNA_372/DIODE                       1.50    2.20   -0.70 (VIOLATED)
_22759_/A                               1.50    2.20   -0.70 (VIOLATED)
_22020_/A                               1.50    2.20   -0.70 (VIOLATED)

How would one go about debugging and potentially fixing those? I have absolutely no clue what _20535_/A is

From grepping in the build results it looks like it's a

sky130_fd_sc_hd__buf_1

but at what point are these numeric identifiers created, and from what?

Ok, so following it backwards it looks like it's my clock that passes through a gazillion clock buffers and then through two regular buffers. This makes me suspect the clock tree synthesis

Metric or imperial gazillion?

Looks like there's a diode hanging on the net. No expert on this flow but perhaps the diode insertion strategy needs to be more aware of affects on slew rate?

Yep. Checked 10 of 34 slew rate violations so far and all of them are on nets with a (inserted?) diode

Okay, well, I updated OpenLane to tag

2021.12.28_01.47.52

and there are still no diodes for the

sky130_fd_sc_hs

family

Hi, I'm trying to harden my design for MPW4 but I every time I'm getting hold violations or capacitance violations. I'm using the OpenLane, efabless version with the MPW4 tag, I'm changing the parameters of PL_RESIZER_HOLD_SLACK_MARGIN,PL_RESIZER_MAX_SLEW_MARGIN,PL_RESIZER_MAX_CAP_MARGIN and PL_RESIZER_HOLD_MAX_BUFFER_PERCENT. But seems the result random every time I launched, some time I get violation in the sta_max other in the sta_min. Any suggestion of how better I can use that parameters, base of the violation time , or If i need another parameter to tweak, to get a hold free result?

Ok, so now I see where my slew time violations are. The question that remains is how to fix them. I guess there is something that automatically inserts buffers on high fanout nets. And since this is a clock signal, I also assume CTS has some logic to decide when to place clock buffers (I see 8 clock buffers in series on the path to the point of failure). On top of that I suspect inserted diodes affect slew rate too. To me, this looks like it would need an interative solution where timing analysis is part of the loop. Looking here https://github.com/The-OpenROAD-Project/OpenLane#openlane-architecture however it seems like the STA is outside this loop, which means that timing results are not fed back to subsequent iterations

Any tips on setting these macro names in the FP_PDN_MACRO_HOOKS env variable.

Hi, I'm trying to do the hardening of the wrapper, but when I launch the "make user_project_wrapper" have an error asking for a file in "caravel/openlane/user_project_wrapper_empty" but that file does not exist, I try to use caravel-lite and caravel, but same result.

We have the following error on precheck "Klayout minimum clear area density check failed". Any tips on correcting would be gratefully received.

Hi <!here> I have a question related to the tools used in OpenLane, Is there any way to run them as a multi threaded to perform the flow in least runtime possible. I have found that we can do this for TritonRoute tool by setting ROUTING_CORES variable, so is it possible for others ?