#670 Max fanout default considered ? Issue closed by vijayank88 The-OpenROAD-Project/OpenLane

#718 Support for overriding the module parameter during synthesis New issue created by dineshannayya Prompt When Generic IP which has multiple parameter over-ride option, it would be better to provide module parameter over-ride during synthesis. Yosys support command to overide the module parameter. HERE is Yosys Example command Memory bits <= 18K; Data width <= 36; Address width <= 14: read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 blockram This module parameter option is not supported in Openlane flow. Proposal Add additional environmental variable like : SYNTH_PARAMS set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 8, BIST_DATA_WD 32, BIST_ADDR_START 9'h000, BIST_ADDR_END 9'h1FB, BIST_REPAIR_ADDR_START 9'h1FC, BIST_RAD_WD_I 9, BIST_RAD_WD_O 9 " Add the following logic in synth.tcl & synth_top.tcl Module level parameter overide if { [info exists ::env(SYNTH_PARAMS) ] } { log "Reading $::env(SYNTH_PARAMS) as a parameter" set records [split $::env(SYNTH_PARAMS) ","] foreach rec $records { chparam -set [lindex $rec 0] [lindex $rec 1] $vtop } } else { log "No parameter define found" } synth.txt synth_top.txt Attached the modified scripts/synth.tcl and scripts/synth_top.tcl Note: File name extension is changes from .tcl to .txt due to github attach error/ Alternatives Currently we have to manually hardcode the paremeter inside the generic module. The-OpenROAD-Project/OpenLane

I thought ROMs were done with standard cells for 1s and 0s, but I've just done some experiements and it seems that yosys is synthesising logic that gives the same output as a ROM. Is that expected?

How do I avoid routing nets in non-default direction in openlane flow?

Hello all, Can somebody provide the syntax for setting the env variable FP_PDN_MACRO_HOOKS for two macros: mprj with vccd1 , vssd1 and temp1 with vdda2 , vssa2. I have currently given as shown in the picture, but still both are getting set to vccd1 & vssd1 only

Hi guys, I would like to confirm something about OpenLane -- If it is true that the parameter "CTS_TARGET_SKEW" is never used in any script? Thanks in advance.

Hello all. I have placed a macro in the user project area and ran the openlane flow. As you see in the picture below there are no power lines in the area where I have placed the macro because of which my macro's power pins or not connected to vdda1 and vssa1. Why does that happen? I have also included the config.tcl file for reference. Thank you in advance.

#725 getting Segmantation fault (core dumped) error during magic compile New issue created by msaideroglu When I try to check spm design test results in /openlane/designs/spm/../results/magic, the result of "magic spm.mag", or "magic -rcfile sky130A.magicrc" it gives -Segmentation fault (core dumped) error The-OpenROAD-Project/OpenLane

#725 getting Segmantation fault (core dumped) error during magic compile Issue closed by msaideroglu The-OpenROAD-Project/OpenLane

The PDN scripts in OpenLane seem broken when using multiple power domains. It can connect only vccd1 and vssd1. I am trying to re-submit our design (with timing errors) from the MPW-2 but the PDN scripts in openlane can't connect the hard macro to vccd2 and vssd2. Do you know any workaround to bypass this? I got this warning: "[WARNING]: All internal macros will not be connected to power." and the power net are not connected". This is my config:

set ::env(FP_PDN_MACRO_HOOKS) "vco_adc_wrapper_1 vccd1 vssd1, vco_0 vccd2 vssd2, vco_1 vccd2 vssd2, vco_2 vccd2 vssd2"
set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
 set ::env(FP_PDN_CHECK_NODES) 0

set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_PDN_ENABLE_RAILS) 0

#303 ROUTING_OPT_ITERS no longer works Issue closed by donn The-OpenROAD-Project/OpenLane

#727 Flow fails when using inverter example with sky130_fd_sc_hvl New issue created by hpretl Description Tried to run the stock

inverter

example, only changed the library in

config.tcl

to

set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hvl"

Run fails on step 2 with: Error: sta.tcl, 42 cannot read file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib . Both files are available and accessible. Not sure if the trailing

.

causes the issue, but I also do not know where this is introduced. Environment

Python: v3.9.7
Kernel: Linux v5.13.0-20-generic
Distribution: ubuntu 21.10
Container Engine: docker v20.10.7
OpenLane Git Version: 2021.11.23_01.42.34
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

commit e1883edfbcc8c7e96491158521522b7a66541745
Author: Manar <manarabdelatty@aucegypt.edu>
Date:   Mon Nov 22 07:59:18 2021 -0600

    Update resizer (#726)

commit 6245b0e675d0e6751bdfc5362c545efe29d1077c
Author: Manar <manarabdelatty@aucegypt.edu>
Date:   Fri Nov 19 13:38:50 2021 -0600

    Fix sram install (#724)
    
    Also disable by default

commit e0e6fbc1bd90d1c73aae19769d997da8c3c47512
Author: Manar <manarabdelatty@aucegypt.edu>
Date:   Fri Nov 19 12:30:08 2021 -0600

    Add option for enabling/disabling repair_tie_fanout (#722)
    
    * Add option for enabling/disabling repair_tie_fanout
    
    * add escape characters
    
    * Add option for enabling sta report power

Reproduction Material I am using the stock

inverter

example in the design folder. Expected behavior Running without fail ?! Logs The-OpenROAD-Project/OpenLane

#729 read_lib fails when trimmed.lib contains two libraries New issue created by hpretl Description After solving #727, the flow script fails further down at step 7. Here, the

read_lib $::env(LIB_SYNTH)

in

replace.tcl

fails, because the file

/openlane/designs/audiodac/runs/RUN_2021.11.23_16.42.33/tmp/trimmed.lib

contains two

library

entries:

line 1:
library ("sky130_fd_sc_hvl__tt_025C_3v30") {

and

line 31779:
library ("sky130_fd_sc_hvl__tt_025C_3v30_lv1v80") {

Environment See #727 Reproduction Material See #727 Expected behavior Not crashing with error. Logs

/openlane/designs/audiodac/runs/RUN_2021.11.23_16.42.33/tmp/trimmed.lib
[ERROR STA-0026] /openlane/designs/audiodac/runs/RUN_2021.11.23_16.42.33/tmp/trimmed.lib line 31779, syntax error, unexpected KEYWORD, expecting $end.
Error: replace.tcl, 57 STA-0026
[ERROR]: during executing: "openroad -exit /openlane/scripts/openroad/replace.tcl |& tee >&@stdout /openlane/designs/audiodac/runs/RUN_2021.11.23_16.42.33/logs/placement/7-replace.log"
[ERROR]: Exit code: 1

The-OpenROAD-Project/OpenLane

#727 Flow fails when using inverter example with sky130_fd_sc_hvl Issue closed by donn The-OpenROAD-Project/OpenLane

#298 OpenSTA unable to finish Issue closed by donn The-OpenROAD-Project/OpenLane

#426 Error in routing stage Issue closed by donn The-OpenROAD-Project/OpenLane

#590 libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib does not exist when trying to do make pdk Issue closed by donn The-OpenROAD-Project/OpenLane

#733 Artifact reorganisation creates bad path during synthesis New issue created by antonblanchard After updating Openlane I hit the following error during synthesis:

ERROR: Can't create file /project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-synthesis.log/2-synthesis_pre.stat.

synth_report_prefix and synthesis_reports are indeed bad:

set ::env(synth_report_prefix) {/project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-synthesis.log/2-synthesis}
set ::env(synthesis_reports) {/project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/synthesis/1-synthesis.log/2-synthesis.log}

It does look like an issue if we call run_yosys twice:

set ::env(synth_report_prefix) [index_file $::env(synthesis_reports)/synthesis]
        set ::env(synthesis_reports) [index_file $::env(synthesis_reports)/synthesis.log]

The-OpenROAD-Project/OpenLane

#735 DRC violations New issue created by rahulrbharadwaj Description I have an analog module which I have layed out in hand using the latest version of magic with no DRC violations. I have called this analog module as a macro in openlane and the ran the flow. At the end of the flow there are DRC violations. Environment

PDK Version Verification Status: OK

Reproduction Material <url|https://drive.google.com/drive/folders/1qruuyWZgdvJDj1c_m4O1XuFW0_pasv9c?usp=sharing> Expected behavior There must be no DRC violations. Logs

The log file is included in the tar compressed file.

The-OpenROAD-Project/OpenLane

#735 DRC violations Issue closed by rahulrbharadwaj The-OpenROAD-Project/OpenLane

#736 Add mechanism to create OpenROAD reproducibles on failure automatically New issue created by donn Prompt I am physically aging trying to get the reproducible for #710. Proposal

try_catch openroad

failures should be automatically detected, and if they happen, or_issue.py should be called to create a reproducible that can be uploaded immediately instead of having to rely on the user to package it or an OpenLane maintainer to do so then pass it on to OpenROAD. The-OpenROAD-Project/OpenLane

#710 Flow crashed at STA Multicorner - segmentation fault in the newest docker image tag: 2021.11.13_01.43.55 Issue closed by donn The-OpenROAD-Project/OpenLane

#735 DRC violations Issue reopened by rahulrbharadwaj The-OpenROAD-Project/OpenLane

#657 Global Placement error: RePlAce diverged at newStepLength Issue closed by donn The-OpenROAD-Project/OpenLane

#737 make pull-openlane failed New issue created by vijayank88 Description Not able to update latest openlane commit. Environment

python3 ./env.py issue-survey
Python: v3.8.10
Kernel: Linux v5.11.0-40-generic
Distribution: ubuntu 20.04
Container Engine: docker v20.10.10
OpenLane Git Version: 2021.11.25_01.26.14
---
PDK Version Verification Status: MISMATCH
The version of open_pdks installed does not match the one required by the OpenLane flow scripts (installed: 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad, expected: c5730b574461889c82858b08d12ba42423d9c2cb)
You may want to re-install the PDK by invoking `make pdk`.
---
Git Log (Last 3 Commits)

commit 287cb3a712f1421097794e480177835383766187
Author: Kareem Farid <kareefardi@users.noreply.github.com>
Date:   Wed Nov 24 21:46:17 2021 +0200

    Verify existence of EXTRA_GDS_FILES (#731)

commit 520f2f136a1cd3e7b99485740b724dadc974eecf
Author: Donn <me@donn.website>
Date:   Wed Nov 24 14:59:08 2021 +0200

    Update OpenROAD, Magic and CVC (#734)
    
    CVC now also points at master instead of @donn's fork

commit 65da365962a942b595d59b64a5dbdbc550cd91cc
Author: Anton Blanchard <anton@linux.ibm.com>
Date:   Wed Nov 24 23:50:31 2021 +1100

    Fix typos in PL_RESIZER_REPAIR_TIE_FANOUT option (#732)
    
    [skip ci]

Reproduction Material

cd openlane/
    git checkout master
    git pull
    export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
    make pull-openlane

Expected behavior complete make pull-openlane complete successfully. Logs

File "./dependencies/get_tag.py", line 26
    process_data: subprocess.CompletedProcess = subprocess.run(["git", "describe", "--tags", "--abbrev=0"], stdout=subprocess.PIPE, stderr=subprocess.PIPE)
                ^
SyntaxError: invalid syntax
Pulling most recent OpenLane image relative to your commit...
docker pull 
"docker pull" requires exactly 1 argument.
See 'docker pull --help'.

Usage:  docker pull [OPTIONS] NAME[:TAG|@DIGEST]

Pull an image or a repository from a registry
make: *** [Makefile:184: pull-openlane] Error 1

The-OpenROAD-Project/OpenLane

#733 Artifact reorganisation creates bad path during synthesis Issue closed by donn The-OpenROAD-Project/OpenLane

Does anyone have problems with editing the drc.tcl in Openlane? I am trying to change srcripts/magic/drc.tcl in openlane source tree but I do not see any change in the log file. Furthermore, I added the code to bypass the DRC checks on SRAM cells but it did not take any effect also. This is the code that I added to drc.tcl:

diff --git a/scripts/magic/drc.tcl b/scripts/magic/drc.tcl
index 5019f2c..d253a36 100755
--- a/scripts/magic/drc.tcl
+++ b/scripts/magic/drc.tcl
@@ -11,7 +11,7 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
-
+puts stdout "Hello world\n"
 if { [info exist ::env(MAGIC_DRC_USE_GDS)] && $::env(MAGIC_DRC_USE_GDS) } {
        gds read $::env(CURRENT_GDS)
 } else {
@@ -32,6 +32,8 @@ set cell_name $::env(DESIGN_NAME)
 magic::suspendall
 puts stdout "\[INFO\]: Loading $cell_name\n"
 flush stdout
+puts stdout "\[INFO\]: Hello world\n"
+flush stdout
 load $cell_name
 select top cell
 drc euclidean on

#737 make pull-openlane failed Issue closed by vijayank88 The-OpenROAD-Project/OpenLane

How does openlane and open-MPW precheck relate to each other? So after doing the layout in magic, I convert it to the GSDII files using openlane, and then run the precheck? I am trying to use the analog_wrapper for my design and did not see OpenLane used in the caravel analog documentation.

One question, will be a MPW4 release of openlane or will be using the MPW3 release?