#658 CTS:: run_resizer_timing stage over-write the Synthesis netlist Issue closed by dineshannayya The-OpenROAD-Project/OpenLane

#660 Expired certificate from klayout.org New issue created by oharboe Description

$ cd docker_build
Step 5/9 : RUN wget <https://www.klayout.org/downloads/CentOS_7/klayout-0.27.3-0.x86_64.rpm>
 ---> Running in 056b38d72b4e
--2021-10-21 13:08:53--  <https://www.klayout.org/downloads/CentOS_7/klayout-0.27.3-0.x86_64.rpm>
Resolving <http://www.klayout.org|www.klayout.org> (<http://www.klayout.org|www.klayout.org>)... 178.77.102.107
Connecting to <http://www.klayout.org|www.klayout.org> (<http://www.klayout.org|www.klayout.org>)|178.77.102.107|:443... connected.
ERROR: cannot verify <http://www.klayout.org|www.klayout.org>'s certificate, issued by '/C=US/O=Let\'s Encrypt/CN=R3':
  Issued certificate has expired.
To connect to <http://www.klayout.org|www.klayout.org> insecurely, use `--no-check-certificate'.

The-OpenROAD-Project/OpenLane

the fixes for the broken halos in common_pdn and clock propogation issues in the opensta setup don't seem to be in the latest tools

will there be a new tag?

for mpw3?

#666 Add asap7 pdk New issue created by oharboe Prompt Add asap7 pdk to the build process Proposal

make pdk

should install asap7 pdk The-OpenROAD-Project/OpenLane

Has anyone used the 

sky130_fd_sc_hvl

 library? When I use that in the openlane flow, during the global placement step it throws an error stating that the 

trimmed.lib

 file has errors and some missing keyword. Is that library specific or is there a problem with my design? I tried to generate gds using 

sky130_fd_sc_hd

 and it was successful. Any help in this direction would be of great help.

#669 Update Yosys New issue created by donn Prompt OpenLane’s SystemVerilog support is restricted by its older version of Yosys. Proposal Yosys should be updated. The issue here is though is that some designs break for reasons I cannot yet discern. This isn’t an MPW3 merge window thing, obviously. The-OpenROAD-Project/OpenLane

Currently trying to get the flow working with a simple comb-only design (the bit manipulation unit of a processor we designed) and having trouble with the flow bombing out at step 18 (fastroute) owing to error GRT-0069 [nice] Diode not found

completely lost as to what could be wrong as the same steps with something like an inverter work

we can provide source or you can repro our work from its repo on GitHub if you don't mind running nMigen w/ OpenLANE flow patches

we're trying with sky130_fd_sc_hs as when we try with the sky130_fd_sc_hd cells it bombs out way earlier (step 8 ) with a segfault

I'm wondering if the max fanout default = 5 setting is considered at all. For example, the default regression output of the zipdiv design shows fanouts > 10 (for all synthesis results): Report: _2003_: 65 Report: _1968_: 68 Report: _0081_: 32 Report: pre_sign: 68 Report: r_busy: 65 Eventually the reason for the slow design performance. I see similar problems on other designs.

#670 Max fanout default considered ? New issue created by cloudxcc I'm wondering if the max fanout default = 5 setting is considered at all. For example, the default regression output of the zipdiv design shows fanouts > 10 (for all synthesis results, including zipdiv.synthesis_preroute.v): Report: _0081_: 32 Report: pre_sign: 68 Report: r_busy: 65 It can be verified by running the design and by making a grep of the above signals on the synthesis results netlists. This is eventually the reason for the slow design performance. I see similar problems on other designs. I'm using a 3 wwek old version and the default regression run commands. If you really need more information (logs) let me know. For fanout analysis I'm using a private (not open-sourced yet) EDA tool. A log wouldn't provide more information than the above. The-OpenROAD-Project/OpenLane

#671 High Clk Skew number observed with Latest OpenRoad CTS Tool New issue created by dineshannayya Openroad version: v2.0-1424-gf864efbae I am trying to harden small design with Openlane flow with MPW-3 Tag. I see Clk Skew number in order of 2.33ns. If if use the same design in Openlane:RC7 tag the skew number are with-in 0.12ns or 130ps 1. Here is the Clock Skew Number with Openroad version: v2.0-1424-gf864efbae Clock bist_clk Latency CRPR Skew _1822_/CLK ^ 3.67 _1704_/CLK ^ 1.34 0.00 2.33 wns -3.88 tns -131.54 Attached the Example Setup: mpw-3.tar.gz 2. Here is result based on RC7 Tag & Clock Skew are in the order of 0.12ns or 130ps Clock bist_clk Latency CRPR Skew _1771_/CLK ^ 0.56 _1794_/CLK ^ 0.44 0.00 0.12 wns 0.00 tns 0.00 Attached the Example Setup mpw-2.tar.gz I have used or_cts.tcl file from openlane for my analysis. One observation: In MPW-3 CTS uses both slow and fast corner library where as MPW-2 CTS uses only one corner Typical corner library .. Not clear is CTS reporting worst violation between two corner (Slow and Fast corner) ? The-OpenROAD-Project/OpenLane

mpw-3 openlane seems to ignore FP_ASPECT_RATIO - anyone else seen this?

regarding the mpw-3 updates to openlane including STA fixes,

Heyho, I'm trying to set up openlane according to these insturctions https://openlane.readthedocs.io/en/latest/#setting-up-openlane but unfortunately when I get to "make test" I get this error... can anyone help me with the setup?

Hello, I'm getting this warning and not sure which would be the correct version of openlane to run for mpw-3, and how do i change the version after installing?

can anyone point me where i will be wrong with this error?...seems like it doesnt found my macro definition which i defined in the user_project_wrapper.v

Can we get some help from @User or @User or @User about what to do about timing violations with new openlane? What do we do to solve them?

Anyone having issues with pulling mpw-3a from docker? https://hub.docker.com/r/efabless/openlane/tags?page=1&name=mpw

Hi all, Can anyone give an insight "detailed placement failed on" warning. I have fp as absolute to 1000×1200 and pl density 0.6. I could understand what the issue? The design occupies only 33% of this given area only.

Hello, Im not sure why im getting this error on running floorplan interactively...

Hi, I recently reinstalled the pdk using the openlane flow, after running make test, I get the following error: Any ideas what the fix is?

Hi all, I am facing segmentation violation in routing phase. Any insights into this issue?

@User has left the channel

After fress OpenLane install

./flow.tcl -design spm

Gives error

[ERROR STA-0402] repair_design -slew_margin is not a known keyword or flag.

??? OH! Please disregard. Found the answer above.

Hi all, after new updates, I am facing "*[ERROR PDN-0165] Conflict found, instance cb_0_0 is part of two grid definitions (CORE_macro_grid_2, CORE_macro_grid_1).*". Can someone point out what are these macro grids?

Hi all, I have a macro in my design and it is a 256-bit OpenRAM SRAM. AFAIU OpenRAM compiler uses rings (i.e. set FP_PDN_CORE_RING to 1) to create the SRAMs. Now I’m wondering to know how can I connect the macro power/ground rings to the wrapper by the OpenLane?