@User (@User): What I do is "ps aux | grep netgen" to get the <pid>, then "gdb program <pid>" to attach a gdb process to it. Then I can see immediately where the program is executing.

that will help for a hangs, also wanted to see overall view, will give those a try

@User: Part of the netgen setup file ignores the decap and fill cells. If you don't do that, netgen goes into a very tedious process of flattening them. However, in the worst case I've seen so far (the striVe SoC core, which was about 2mm x 2mm or more), it only ran for maybe 10 minutes at most. With eight hours, it seems most likely that something else is going on.

Yeah, I think it's just stuck in an infinite loop.

Watching the fossi talk now. Great intro to the design steps and what the file formats are. Never heard it so clearly before

What does hardening mean in relation to ASICs?

@User: "Hardening" generally means taking a design and running it through place and route and generating all the various files (LEF, GDS, SPICE, etc.) needed for it to be treated as a "hard macro" block in a larger design (anywhere in the hierarchy up to the chip top level).

Did openlane switch from EF_STYLE=1 to EF_STYLE=0 from

rc1

to

rc2

?

i think so 🙂

@User and @User I found something which I think is a bug between @User's open_pdks repo and the openlane open_pdks fork, if you are interested I can explain

Ok, got

rc2

running \o/

@User: We're currently in the process of merging the needed changes properly into the original repo, so sure interested what bug you found.

@User: There are two open items which I have not merged yet, so just check the open_pdks Issues page on github to check if it's related. . . which it likely is (I'm essentially merging all the changes that Ahmed made, but there were a few minor issues).

@User i passed on the info to @User

basically your repo is actually doing the right thing as far as I can tell

picorv32a

sorry my magic skills are terrible...

its also a little bit of a hog on a design that size it seems

@User Did netgen finish for you ?

@User you mean Circuit 1 contains 75500 devices, Circuit 2 contains 75500 devices. Circuit 1 contains 17710 nets, Circuit 2 contains 17710 nets. Circuits match with 11483 symmetries. Netlists match with 11478 symmetries. ?

Yeah.

not really sure that's what I would call finish ...

but it "worked" ...

that's another small hog of IO resources

I’m in the process of getting hooked on magic, worked fine on my block with 100k devices… makes me remember getting started on vi

seems like it takes forever to finish writing out something....

@User Here it takes hours to finish that process.

@User how long was your routing step ?