set the channel description: EDA community exploring machine learning ML VLSI CAD, studies only generate small internal datasets for validation for lack of large public datasets. We present the first open- source dataset called CircuitNet for ML tasks in VLSI CAD.

CircuitNet is an open-source dataset dedicated to machine learning (ML) applications in electronic design automation (EDA). We have collected more than 20K samples from versatile runs of commercial design tools based on open-source designs with various features for multiple ML for EDA applications. This documentation is organized as followed: • Introduction: introduction and quick start. • Feature Description: name conventions, calculation method, characteristics and visualization. The codes in the tutorial page is available in our github repository https://github.com/circuitnet/CircuitNet.

The gate-level netlists are the ones used in data generation. They are synthesised from 6 RISC-V designs with commercial 28 nm library and Synopsys Design Compiler(DC) with multiple variations. (see page Feature for detailed information about variations) The name of standard cell and IP is encrypted due to copyright issue. There are 2 version of netlist, one is the original hierarchical version written by DC, and the other one is the flatten version written by Innovus for extracting graph. *For ease of use, we extract the necessary information for forming graph from the flatten netlist.*They are saved in the form of numpy array in graph_information.tar.gz. (1) Pin Attributes: pin names, corresponding net index, node index. (2) Net Attributes: net name. (3) Node Attributes: node(instance) name, corresponding standard cell / IP name. The array can be loaded with

numpy.load(FILE_NAME, allow_pickle=True)

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