set the channel description: IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE) - “Code-a-Chip” Travel Grant Awards at ISSCC'23 (https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io)

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Hello, I would like to know if I can use VHDL instead of VERILOG on openlane. Thanks :D

Basic example of running Ngspice with SkyWater models in a Colab notebook. https://github.com/bmurmann/Ngspice/blob/main/Ngspice.ipynb

@Boris Murmann @mehdi is there a chance there will be an extension for submitting the code-a-chip notebook?

<!here> Due to multiple requests. We have decided to extend the deadline to the 25th Nov. so that hopefully you have enough tome to review your submissions. Thanks!

@Jorge Marin can you tell me who is the lead on your submission? https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io/blob/main/Notebooks/3LFCC/3Level_Flying_Cap_Converter.ipynb

Many thanks, everyone, for your participation! We recommend resubmitting your Notebooks to the next code-a-chip Notebook competition with revisions. Stay tuned! Please check out the list of accepted Notebook: https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io

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<!here> The next CAC Notebook Competition at VLSI 2023 CFP is up! Please consider submitting your ideas as a Notebook and get a chance to attend the VLSI Symposium 2023 in Kyoto! https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io

Does anybody know if there is a meeting link for the info session (mentioned on the Github page) this Wednesday? Or is it yet to come? Thanks! :)

Thanks Kennedy. Here is the link: “Code-a-Chip” Travel Grant Awards Info Session Topic: “Code-a-Chip” Travel Grant Awards Info Session Time: Feb 15, 2023 11:00 AM Eastern Time (US and Canada) https://us06web.zoom.us/j/89374924775?pwd=YXQzUHp5TVpmRTh5eFo4YW1FK0lxUT09

<!here> Info session for code-a-chip is happening now: “Code-a-Chip” Travel Grant Awards Info Session Topic: “Code-a-Chip” Travel Grant Awards Info Session Time: Feb 15, 2023 11:00 AM Eastern Time (US and Canada) https://us06web.zoom.us/j/89374924775?pwd=YXQzUHp5TVpmRTh5eFo4YW1FK0lxUT09

Slides from today's info session:

I saw a presentation about "Chip-To-Chip integration" in the ISSCC2023 evening session (EE2) presented by Asako Toda-san. She is from Intel, who showed us the use case of open-source. She said the power reduction of bus I/F for inter SiP comm was successful.

I was thinking about submitting a notebook that uses the gm-Id method for analog design, was there something like this before?

Hello @Boris Murmann @mehdi, For our Code-a-Chip project we have aimed to use Jupyter inside the IIC-OSIC-TOOLS Docker Container. With the help of @Harald Pretl and his team we have been able to work like that, but there are still some issues. When we use Firefox from within the container, it works very slowly and consumes a lot of resources. We are currently using a workaround, with the root user of the container we allow a browser from the host computer to display the interface of Jupyter, which runs inside the container. Right now, the docker might not be the best solution to make the notebook user-friendly, but we can expect it to work better in the future. Should we look for another alternative and have the notebook install all the tools we need (analog flow)? or could we submit the notebook like this? The deadline is near and we prefer to spend more time improving the content of our project.

Hello @mehdi and @Boris Murmann, I hope you are doing fine Do you have any news on the contest results?

<!here> The results are out! https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io/tree/main/VLSI23 Thanks for all your contributions!

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