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- a
Alexander Shabarshin
12/05/2022, 11:47 PM@Alexander Shabarshin has left the channel - s
Sean Cross
12/13/2022, 9:32 AMHi all, are there any examples of how to use the SRAM macros? Is it just a matter of adding the simulation Verilog to my
, or is there something extra I need to do? Something with blackboxing it, perhaps?VERILOG_FILES - s
Sean Cross
12/13/2022, 9:33 AMYosys (via OpenLane) is, rightfully, complaining about `...in cell\gf180mcu_fd_ip_sram__sram512x8m8wm1' is not part of the design. - s
Sean Cross
12/14/2022, 1:38 AM@Sean Cross has left the channel