@Alexander Shabarshin has left the channel

Hi all, are there any examples of how to use the SRAM macros? Is it just a matter of adding the simulation Verilog to my

VERILOG_FILES

, or is there something extra I need to do? Something with blackboxing it, perhaps?

Yosys (via OpenLane) is, rightfully, complaining about `...in cell

\gf180mcu_fd_ip_sram__sram512x8m8wm1' is not part of the design.

@Sean Cross has left the channel

I have been able to successfully setup gf180 pdk using Volare through steps given in below YT link. Can anyone clarify what needs to be done if another design needs to done with sky130 pdk. What needs to be done with volare setup or environment variables $PDK_ROOT and $PDK. Can both PDKs i.e. gf180 and sky130 be accessed simultaneously using Volare to open two separate designs in parallel?

@Abdulaziz has left the channel

@Sebastian Sanchez has left the channel

@Nuno Lourenço has left the channel