@User https://github.com/google/skywater-pdk#sky130-process-node

Excellent, thanks.

there is a lot to digest

@channel Free Demo of Physical design, RISC-V and System Design Workshop As you might be aware of below last 4 workshops of this year, for people who had already attended our previous workshops, are aware of the flow. (5-day) Nov 18-22' 2020 - Beginner Physical Design, qflow/OSU180, By Kunal Ghosh, IIT Bombay Alumni, Founder VSD Corp. Pvt. Ltd. (5-day) Nov 25-29' 2020 - Advanced Physical Design OpenLANE/Sky130, By Kunal Ghosh, eFabless team and Nickson (5-day) Dec 2-6' 2020 - RISC-V using TL-Verilog, By Steve Hoover, Founder, Redwood EDA (1-day) Dec 9' 2020 - System design using Verilog, Prof. V Kamakoti, IIT Madras Here's the link with registration details: https://www.vlsisystemdesign.com/vsd-iat/ But for people, who are joining our workshops for first time, we are arranging 1-hr demo for all workshops on 11 November, 7pm to 8pm IST. If you want a reminder for the same, fill-up below google form, and we will send you meeting invites https://forms.gle/E4qeBAXZuf6nNy3GA FEEL FREE TO FORWARD THIS MESSAGE TO YOUR NEEDY FRIENDS IN CASE THEY ARE LOOKING FOR VLSI JOBS OR WANT TO LEARN LATEST IN AREA OF OPEN-SOURCE VLSI AND RISC-V

Can people check if they can see the sky130_fd_io library at https://foss-eda-tools.googlesource.com/ ?

I can see it

<!channel> - Everyone should make sure to join the skywater-pdk-announce mailing list at https://groups.google.com/g/skywater-pdk-announce so you don't miss any important announcements.

It's very low volume

has there been any discussion yet on the carrier PCB?

@User I'm not sure if there's going to be one or not? should be fairly simple to lay one out and it would be useful to have...I was out of the discussions for a while though so it may have been discussed a couple weeks ago

@User IIRC a handful of carrier PCBs with castellated holes was mentioned at one point.

I believe there's enough info on the ball layout and pinouts for caravel to layout a useable PCB...If you put one up on github it would be useful at least as a starting point for projects requiring a more tuned layout...

stan56mufifn

Is there somewhere I could purchase physical chips that have an open source design? (i.e. have already been through Openlane or will be going through the fab process?)

Preferably at the 130 nm node

@User there hasn't been a run for sky130 yet so there are no chips to obtain. when the first shuttle is complete, the various project owners will receive a number of chips which they can distribute as they see fit...the idea is that someone wanting to test or do something with a particular project's design can just ask and there will enough chips to send you one

if you're looking for a specific design that you want manufactured, you'd go direct to skywater or to a design house like efabless

the first shuttle run is likely to contain individual cells for testing and characterization and will therefore not be "useful" as an end product

@User Appreciate the response! I understand that the tapeout for sky130 is planned to happen soon…wanted to also see if there was anything else that already existed out there. I’d like to test with someone’s design and individual cells would be sufficient, so if there are chips to spare I would certainly appreciate it. Thanks!

Has the timeline been published for this tapeout? i.e has the deadline to submit designs closed and how long is the process expected to take?

one of the goals of the project is to be able to iterate designs and build on designs. This motivates google paying for the shuttle runs and generating a number of chips for each design. Their stated goal is that if someone is interested and since you can't easily recreate a project like you can with software or even a PCB design, there should be devices available to give away. The details will be left to the project owners but I suspect they'll send you some for free or cost of shipping

@User when is the deadline to submit design blocks for this shuttle run?

November 30

How to submit the design?

For this shuttle run?

We will generate several versions of OTAs we want to characterise.

Sorry for asking just joined.

@User they have not yet opened the shuttle submissions, but the requirements are that the design must fit into the caravel harness structure (specifically in terms of I/O and area config), and that the hardened macro has to be buildable by openlane into the final SoC