Can anyone recommend a good python module for processing vcd (value change dumps) from e.g. icarus verilog?

There's pyvcd

Workshop on Open Source EDA Technologies (WOSET) 2020 papers and presentations are now available: https://woset-workshop.github.io/WOSET2020.html

@User: Can you do one little thing and change the column "Article #" on the github.io site with the author name? The article number does not seem to be especially relevant now that the submissions are done, and I'd like to see who is the speaker on the front page (I'd like to say I am totally unbiased and will systematically go through every talk and watch the full video, but that is sort of pending on me having the time to watch all of them). One more thing: The title still says "Tentative Schedule", but I assume the schedule is now final?

A13, automatic schematic generation, looks neat; don't remember that one being mentioned here!

Please register for the live part of the Workshop on Open-Source EDA Technologies (WOSET) webinar here! https://ucsc.zoom.us/webinar/register/WN_fEhWeO0BTFaZbQ3i5z9jEw?t=1603989488987

[PDF] ExPAN (N) D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems S Nambi, S Ullah, A Lohana, SS Sahoo, F Merchant… - arXiv preprint arXiv …, 2020 The recent advances in machine learning, in general, and Artificial Neural Networks (ANN), in particular, has made smart embedded systems an attractive option for a larger number of application areas. However, the high computational complexity, memory footprints, and energy requirements of machine learning models hinder their deployment on resource-constrained embedded systems. Most state-of-the-art works have considered this problem by proposing various low bit-width data representation … •Cites: ‪Adaptive Posit: Parameter Aware Numerical Format for …‬

I added data on the newly-landed OSU cells to the table here http://diychip.org/sky130/ . For those who missed the FOSSI talk, they are doing high/medium/low for different track sizes. The 18T and 15T are there now. I have linked the documentation on the cells which includes rise and fall times and power consumption numbers. The Spice models for the cells have extensive parasitic extraction.

<https://github.com/thesourcerer8/OpenSourceTCAD/%7Chttps://github.com/thesourcerer8/OpenSourceTCAD/ <-- now supports Genius, DevSim and Charon>

New channel created recently: #shuttle-precheck

Last Workshop of 2020 - SoC/Physical design using OpenLANE/Sky130 from 25th - 29th November'2020 Here's the registration link for the same: (Read FAQ's before enrolling) https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/ Make sure, by end of this year, you learn something new and exclusive Make sure you learn so much that you are indispensable Note - I am also still learning

Hi, I am new to this channel and actually new to slack. I have 10+ experience in digital design (RTL and verification) on both FPGA and ASIC.

I would like to learn more about ADPLL (all digital PLL) design, I started with Google, reading a few articles.

There is an ADPLL example in the openlane repo https://github.com/efabless/openlane/tree/master/designs/digital_pll_sky130_fd_sc_hd I would like to study it before I start experimenting.

I would probably be able to run Verilog simulations of a timing annotated netlist using Icarus Verilog, but I assume DCO timing would not be accurate.

So I am looking to run a spice simulatio, Since I do not have much spice experience I would like some help finding some example/instructions, preferably something sky130 and openlane specific

I will be back in about 2h, I am going out, there aren't many opportunities to be in the sun during quarantine.

@User: I have called it an "all-digital PLL" but actually it is an all-digital frequency-locked loop. I can post the design files including the ngspice netlists for simulation.

@User Any idea why you haven't done that already?

yes please I did read the comments so I do know it is a frequency-locked loop

Is this the same PLL/DLL to be used in the template (I think you call it harness)?

If you look at the separate thread above, I was able to run openlane builds for the PLL and I tried to use the inverter to refresh my spice knowledge. I found an issue I will report (of course it is possible I did something wrong).

Here is a script that will list the mag cells with port conficts.

#! /bin/bash
  
awk '
/label/ {
    label = $NF;
}
/^port/ {
    print FILENAME, label, $2;
}
 {
    if ( last_file != $1 ) {
        last_file = $1;
        count = 1;
    } else {
        count = count + 1;
    }
}' $* | \
    sort -u -k1,1 -k3,3n | \
    awk '
 {
    if ( last_file != $1 ) {
        last_file = $1;
        count = 1;
    } else {
        count = count + 1;
    }
}
$NF != count {
    print $0, count;
}'

I named it

check_ports

and ran it as

check_ports *.mag

@User I wonder if we can add that to the skywater-pdk CI in some way?

@User Sorry, I posted in the wrong channel. Was supposed to be in a private conversation.

@User That sounds like something which should be in a public conversation? The more we share how people are doing things the more we all learn!

Plus finding mag cells with port conflicts sounds like a pretty useful thing to be doing.

@User Is live right now talking about going zero to ASIC at https://www.twitch.tv/hackadaytwo

What’s in the PDK? Standard cells with spice models? Design rules?