Run the command below in a clean new directory and after a 350MB download you will dropped into a shell with the openlane flow.

docker run -it -v $(pwd):/openLANE_flow/designs/spm/runs -u $(id -u $USER):$(id -g $USER) diadatp/openlane_pdk:rc2

After that you could run the following to harden the spm design.

./flow.tcl -design spm

I've tested this on Ubuntu 18.04 and its mostly used as a reproducible build environment for remote VMs.

Excellent!

what's the best practice for bias voltages on multiple fets in a cell? Should I setup voltage rails for them and connect outside the cell (to either an external voltage, on-chip converter, or Vref as appropriate)?

if so, is there a generally used layer for voltage rails? (metal1?)

finally, best way to connect that to the poly or locali for the fets? (magic via1/via2, etc. menu items?)

or just leave the sub-cell as locali and on the upper cell layer deal with the rails? (same question about vias)

I have a project project for anyone who is interested in learning about yosys and skywater-pdk

I would like to know the maximum clock frequency you could get for a Xbit register -> Xbit register transfer using the different standard libraries -- then put various circuits between the registers (32bit NAND, 32 bit adder, etc) and measure the theoretical fastest frequency given only the gate delays

I have been documenting features of the factory standard cell libraries mainly to identify cells suitable for analog design. The table at the bottom of this might be helpful for anyone trying to get a quick idea of how the performances differences of the libraries were achieved: http://diychip.org/sky130/

Hi there, Did I miss anything?

@User Could we target for that to get into the skywater-pdk documentation?

@User I copied your table into a spreadsheet at https://docs.google.com/spreadsheets/d/1il_87E5sJ2WKciwEPlG8IymWsnheIlpBkUOxmTkHWyA/edit#gid=0

@User Can probably help there

I'm assuming um means nanometer in that document

My bad: I should have put units in on the original document. I have fixed Tim’s version.

Any #Cryogenic experiences? Running 130, ... at 78K, 77K, 4k? Thanks!

@User Tim added some interesting prompt columns for nand2 nand4 and dff. I haven’t checked every library yet but generally nand2 and nand4 are built with the same size transistors as the inverters. The flip flops mostly uses the same size but the internal weaker hold cells have smaller transistors. These metrics beyond the basic ones I did by hand are best derived with some code. Perhaps the table will usefully be populated by some gate delay estimates and cell size numbers?

@User I know that skywater has some experience with that

BTW The model names in the published primitives will be different

@User has there been any additional guidance on licenses?

i.e. which are compatible with the pdk and shuttle?\

I know there was mention that GPL will "probably" be fine..what about LGPL (I assume if GPL ends up being ok, LGPL probably will as well)

Preferred and guaranteed is still Apache 2. If you don't want that, probably just use straight GPL to be safe for November

I intend to use Apache 2 for my stuff but there are proven cores (often FPGA proven) on opencores that are often gpl and lgpl

If there's an lgpl library you want to use, it's trivial to just upgrade to gpl for your stuff

If anyone has an interesting open source EDA contribution, please consider submitting a paper to WOSET (Workshop on Open Source EDA Technologies): https://woset-workshop.github.io/ due Sept 6, 2-4 pages

Date: Tuesday, August 25, 2020 Time: 16:00 GMT (time zone converter) Mohamed Kassem - The striVe RISC-V SoC Family on SkyWater 130nm Apache 2.0-Licensed Software to Silicon For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)'s that have been completely developed using an open source process technology, open source IP and open source design automation environment. In a collaborative effort with Google and SkyWater, efabless' team has designed and implemented the striVe SoC family using SkyWater's SKY130 130nm process, efabless' OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks - all of them are available under the Apache 2.0 license. Mohamed will present the striVe open source SoC family with its 6 configurations which will be publicly released to the design community as concrete designs currently on their way to manufacturing. Being truly FOSS and foundry-enabled, the striVe SoC family will serve as physical demonstrators and be the seed for countless community-defined and striVe SoC's stretching the limits of innovation and to serve select commercial markets.

BREAKING: Workshop on Open-Source EDA Technologies (WOSET) 2020 now open for 5 minute "Work in Progress" videos! Don't want to write paper? Submit a video of your open-source EDA/hardware project instead. (Also, WOSET is virtual and free!) https://woset-workshop.github.io

Hello everyone! I am Nikhil Garg, a final year undergraduate student at BITS Pilani, India. I am very interested in in memory computing with memristors. I want to work on incorporation of such devices with the PDK. Is there anyone working along those line with whom I can work? I have some experience with simulating memristors in SPICE but totally new to PDK etc.