Tim Edwards
02/20/2021, 1:56 AMJean
02/21/2021, 12:26 AMTim Edwards
02/22/2021, 1:07 AMMitch Bailey
02/22/2021, 3:52 AMsram_1rw1r_32_256_8_sky130
, SRAM_0 and SRAM_1.
SRAM_1 has unconnected inputs that may be Hi-Z input to logic (particularly clk1
looks like it's input to an inverter).
Here is the verilog from verilog/rtl/storage.v
sram_1rw1r_32_256_8_sky130 SRAM_0 (
.addr0(mgmt_addr),
.addr1(mgmt_addr_ro),
.clk0(mgmt_clk),
.clk1(mgmt_clk),
.csb0(mgmt_ena[0]),
.csb1(mgmt_ena_ro),
.din0(mgmt_wdata),
.dout0(mgmt_rdata[31:0]),
.dout1(mgmt_rdata_ro),
.gnd(VGND),
.vdd(VPWR),
.web0(mgmt_wen[0]),
.wmask0(mgmt_wen_mask[3:0])
);
sram_1rw1r_32_256_8_sky130 SRAM_1 (
.addr0(mgmt_addr),
.addr1({ _NC1, _NC2, _NC3, _NC4, _NC5, _NC6, _NC7, _NC8 }),
.clk0(mgmt_clk),
.csb0(mgmt_ena[1]),
.din0(mgmt_wdata),
.dout0(mgmt_rdata[63:32]),
.dout1({ _NC9, _NC10, _NC11, _NC12, _NC13, _NC14, _NC15, _NC16, _NC17, _NC18, _NC19, _NC20, _NC21, _NC22, _NC23, _NC24, _NC25, _NC26, _NC27, _NC28, _NC29, _NC30, _NC31, _NC32, _NC33, _NC34, _NC35, _NC36, _NC37, _NC38, _NC39, _NC40 }),
.gnd(VGND),
.vdd(VPWR),
.web0(mgmt_wen[1]),
.wmask0(mgmt_wen_mask[7:4])
);
You can notice that SRAM_1 is missing the following inputs
clk1
csb1
Also addr[0:7]
are inputs defined as not connected.Tim Edwards
02/23/2021, 3:05 AMMatthew Guthaus
02/24/2021, 12:15 AMMatthew Guthaus
02/24/2021, 12:17 AMmkk
mkk
mkk
Mitch Bailey
02/24/2021, 5:15 AMsky130_ef_io__com_bus_slice_10um
sky130_ef_io__com_bus_slice_1um
sky130_ef_io__com_bus_slice_20um
sky130_ef_io__com_bus_slice_5um
sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
sky130_ef_io__corner_pad
sky130_ef_io__disconnect_vccd_slice_5um
sky130_ef_io__disconnect_vdda_slice_5um
sky130_ef_io__gpiov2_pad_wrapped
sky130_ef_io__vccd_lvc_clamped2_pad
sky130_ef_io__vccd_lvc_clamped_pad
sky130_ef_io__vdda_hvc_clamped_pad
sky130_ef_io__vddio_hvc_clamped_pad
sky130_ef_io__vssa_hvc_clamped_pad
sky130_ef_io__vssd_lvc_clamped2_pad
sky130_ef_io__vssd_lvc_clamped_pad
sky130_ef_io__vssio_hvc_clamped_pad
Tim Edwards
02/25/2021, 4:18 PMnetgen
and dropped the following Python script into it:Tim Edwards
02/25/2021, 4:20 PMTim Edwards
02/25/2021, 4:28 PMMitch Bailey
02/25/2021, 5:56 PMsky130_fd_pr__special_pfet_pass
is not being extracted. Is this a tech file problem?
Here's a link to the netlist for the sram module.
https://github.com/efabless/sky130_sram_macros/blob/sky130_name_mapping/sram_1rw1r_32_256_8_sky130/sram_1rw1r_32_256_8_sky130.lvs.converted.spMatt Venn
03/11/2021, 11:36 AMMatt Venn
03/11/2021, 11:36 AMMatt Venn
03/11/2021, 11:36 AMCamilo
03/11/2021, 1:02 PMmgmt_soc
https://github.com/efabless/caravel/blob/master/verilog/rtl/mem_wb.v, I would like also to read and write memory via wb from firmware, so I assume this would work using almost the same as in mgmt_soc
. So the most simple way I could get around so far is only with reg [31:0] RAM[(64*COLS)-1 : 0];
based on DFFRAM repo and some ideas-modifications from microwatt caravel repo, here is my version of it https://github.com/tucanae47/mem_test_caravel/blob/main/src/DFFRAM.v
I have trouble understanding that code Matt just pointed out and also there are a few things I'm not sure how to fix, for example, according to the smallest size example I found in DFFRAM repo I need to use set ::env(DIE_AREA) "0 0 1000 800"
. Here is my current config version https://github.com/tucanae47/mem_test_caravel/blob/main/config.tcl#L13,
and the best results after processing-hardening are in the picture but would like to get it smaller, I'm part of the course with Matt and there we only have "300 300" . Also, I'm missing to test exploration tool with area size. (which will be the next step), but if any suggestions or hints please do 🙂Ben Newhouse
03/12/2021, 1:46 AMBen Newhouse
03/12/2021, 1:48 AMBen Newhouse
03/12/2021, 2:11 AMBen Newhouse
03/12/2021, 2:23 AMJørgen Kragh Jakobsen
04/07/2021, 3:02 PMPhilipp Gühring
04/16/2021, 11:59 AMKartik Prabhu
04/19/2021, 6:00 PMmake uncompress
and make pdk
(using Magic version 8.3.116, which is >= 8.3.60). Inside OpenLANE, I'm installing it with make openlane
Then, after mounting docker and navigating to the Caravel folder, I run make
, which creates the gds, and I try to run DRC with make drc-caravel
. I get a very large number of violations (COUNT=11519255) on 67 different rules, but according to the documentation, I should be getting 0.
Any ideas on what's going on here? Should I be using different versions?Tim Edwards
04/19/2021, 8:19 PMTim Edwards
04/19/2021, 8:28 PMuser_project_wrapper
is now decoupled from the main caravel
repo, so I assume you can get started without the update to caravel, since the project wrapper is ready to go. There will be a "caravel lite" repository with just the parts needed for simulation and verification so you don't have to pull the full caravel repository for basic digital system integration.Kartik Prabhu
04/21/2021, 7:25 PMmake pdk
. It's been stuck at:
Creating magic generation script to generate magic database files.
Running magic to create magic database files.
for several hours. I'm using the commits specified in the Makefile for skywater and open_pdks. Any ideas?Philipp Gühring
04/21/2021, 9:48 PM