Weston Braun
05/20/2021, 9:37 PMyrrapt
05/22/2021, 11:27 AMsky130_fd_pr.gds
there is 20v0 ESD FETs but the other voltages, particularly 1.8 V are not present.
Do you think it's possible to include the sky130_fd_pr__esd_nfet_01v8
layout in the PDK? Or maybe it already is in there and I've missed it?
Thanks in advanceyrrapt
05/22/2021, 11:53 AMcaravel_bump_bond
layout be reused for MPW2?
ie. if I arrange my floorplan to avoid the RDL routing based on the layout in the repo that will hold for MPW2?Weston Braun
05/27/2021, 9:57 PMJohn Kustin
05/27/2021, 10:06 PMchecks/
and to be honest, couldn't get much from them except there's exactly 1 discrepancy. I couldn't see anything on the .png
either.
Since the full_log.log
is quite long, here's a snippet of the relevant section:
Step 4 done without fatal errors.
Executing Step 5 of 6: Executing XOR Consistency Checks.
Running XOR Checks...
Total XOR differences = 1
XOR Checks on GDS Failed, Reason: XOR Differences count is 1. Please view /tmp/kustinj/ee272bclone/caravel_user_project_analog/checks/*.xor.* for more details.
TEST FAILED AT STEP 5
I've opened up the .xor.gds, selected the top cell (XOR), and tried to select any paint and could select none.
Specifically, what does
XOR differences: 1
"_output" in: xor.drc:41
Elapsed: 0.010s
mean?John Kustin
05/27/2021, 10:33 PMuser_analog_project_wrapper.mag
(the one with the example_por cell) I see the analog IO connection to io_analog[4]
along with the connected io_clamp_high[0]
. This is what I understand to be the primary ESD protection provided by the "undedicated power/analog pad" (referencing slide 6 of @User’s caravan presentation). Am I getting that right? On magic I can't actually see any ESD circuitry on this pad (attached screenshot) Should I be able to? Sorry if my understanding is plain wrong, but I'm not clear on whether or not I have to manually add my own ESD circuitry for io_analog[4]
.John Kustin
05/28/2021, 6:12 PM/*
* I/O mapping for analog
*
* mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
* mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
* mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
* mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
* mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
* mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
* mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
* mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
* mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
* mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
* mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
* mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
* mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
* mprj_io[24] --- --- user_analog[10]
* mprj_io[23] --- --- user_analog[9]
* mprj_io[22] --- --- user_analog[8]
* mprj_io[21] --- --- user_analog[7]
* mprj_io[20] --- --- user_analog[6] clamp[2]
* mprj_io[19] --- --- user_analog[5] clamp[1]
* mprj_io[18] --- --- user_analog[4] clamp[0]
* mprj_io[17] --- --- user_analog[3]
* mprj_io[16] --- --- user_analog[2]
* mprj_io[15] --- --- user_analog[1]
* mprj_io[14] --- --- user_analog[0]
* mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
* mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
* mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
* mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
* mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
* mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
* mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
* mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
* mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
* mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
* mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
* mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
* mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
* mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
*
*/
do`user_analog[0], . . ., user_analog[3], user_analog[7], . . ., user_analog[10]` correspond to the gpio_analog with esd (pad_a_esd_0_h) in the standard I/O cell?
on second thought, those user_analog[*]
are the 11 repurposed GPIO pads, right? if I want to access the old GPIO pins as an analog in/out, I should use these kinds of pins:
* mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
but make sure to configure them appropriately? I wanna make sure I configure my functional verilog model correctly 🙂
i might've been reading this pin list wrong... does "gpio_analog/nosed" mean you can get either "gpio_analog" or "gpio_nosed"? this makes the most sense to meJohn Kustin
05/28/2021, 6:13 PMWeston Braun
05/29/2021, 3:13 AMWeston Braun
05/29/2021, 3:15 AMTim Edwards
05/29/2021, 2:46 PMJohn Kustin
05/29/2021, 9:58 PMsky130_fd_pr__res_generic_po
? this is the extracted model from sky130_fd_io_res75only_small
which is in the gpiov2 cellJohn Kustin
06/01/2021, 5:09 PMViolation Message "Deep N-well spacing < 6.3um (dnwell.3) "found 47 Times.
Violation Message "Deep N-well spacing to N-well < 4.5um (nwell.7) "found 288 Times.
Violation Message "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7) "found 55 Times.
DRC Checks on GDS Failed, Reason: Total # of DRC violations is 390
in a region which doesn't make sense to me. The violating areas start out in my PNP array, but veer way off from any relevant part of the design. When I check my layout with drc(full)
(I select all area and do DRC Update
) I don't get any violations. I read some of `open_pdks/sky130A/libs.tech/magic/sky130A-GDS.tech`and saw that it mentions Generally, this covers rules not found in sky130A.tech
. In any case, I don't understand why I would need any deep nwell for parasitic PNPs.mehdi
06/09/2021, 4:30 PMDan Fritchman
06/11/2021, 12:29 AMuser_analog_project_wrapper
pin locations?
(We’ll be generating a subset of it via PnR - ideally going right to its digital-facing pins)Estelle He
06/12/2021, 6:26 PMuser_analog_project_wrapper
, we encountered this error warning about place_pins -pin_name
. However, we checked that in the or_ioplace.tcl
the line has place_pin
instead. Has anyone seen this error before or know how to fix it? The openlane image is at current
, and we got the same error msg even when running on the given analog example design.
[ERROR STA-0402] place_pins -pin_name is not a known keyword or flag.
Error: or_ioplace.tcl, 96 STA-0402
[ERROR]: during executing: "openroad -exit /project/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl |& tee >&@stdout /project/openlane/user_analog_project_wrapper_empty/runs/user_analog_project_wrapper_empty/logs/floorplan/3-ioPlacer.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
Tim Edwards
06/12/2021, 7:31 PMWeston Braun
06/12/2021, 7:59 PMTim Edwards
06/12/2021, 8:04 PMWeston Braun
06/12/2021, 8:05 PMCircuits match with 16 symmetries.
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.
Result: The top level cell failed pin matching.
Weston Braun
06/12/2021, 8:05 PMWeston Braun
06/12/2021, 8:05 PMEstelle He
06/12/2021, 11:55 PMcommon_pdn.tcl
in pdks but it still didn’t help. Do you have idea how to fix this?
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /tmp/estel/openlane/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_analog_project_wrapper
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Core Rings
Layer: met4 - width: 3.000 spacing: 1.700 core_offset: 14.000
Layer: met5 - width: 3.000 spacing: 1.700 core_offset: 14.000
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 3.330 offset: 0.000
Straps
Layer: met4 - width: 3.000 pitch: 180.000 offset: 5.000
Layer: met5 - width: 3.000 pitch: 180.000 offset: 5.000
Connect: {met4 met5} {met1 met4}
Type: macro, macro_1
Macro orientation: R0
Straps
Layer: met5 - width: 1.000 pitch: 3.000 offset: 2.000
Connect: {met4 met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034] - grid for instance mprj.prbs
[INFO] [PDNG-0015] Writing to database
-code 1 -level 0 -errorcode NONE -errorinfo {invalid command name "NULL"
while executing
"builtin_unknown NULL setSpecial"
("uplevel" body line 1)
invoked from within
"uplevel 1 builtin_unknown $args"
(procedure "sta_unknown" line 36)
invoked from within
"$bterm setSpecial"
(procedure "export_opendb_power_pin" line 9)
invoked from within
"export_opendb_power_pin $net_name "POWER""
(procedure "export_opendb_power_pins" line 6)
invoked from within
"export_opendb_power_pins"
(procedure "opendb_update_grid" line 5)
invoked from within
"opendb_update_grid"
(procedure "apply" line 7)
invoked from within
"apply $config"
(procedure "pdngen::apply_pdn" line 14)
invoked from within
"pdngen::apply_pdn $config_file $verbose "} -errorline 9
[CRIT] [PDNG-9999] Unexpected error: invalid command name "NULL"
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_pdn.tcl |& tee >&@stdout /project/openlane/user_analog_project_wrapper/runs/user_analog_project_wrapper/logs/floorplan/10-pdn.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
Dan Fritchman
06/13/2021, 5:37 PMuser_project
been published anywhere?Weston Braun
06/14/2021, 1:01 AMTim Edwards
06/14/2021, 1:14 AMWeston Braun
06/14/2021, 1:27 AMNetlists match uniquely.
Circuits match correctly.
Result: The top level cell failed pin matching.
Logging to file "comp.out" disabled
Weston Braun
06/14/2021, 1:28 AMWeston Braun
06/14/2021, 1:33 AMNetlists match uniquely.
There were property errors.
Parallelized instances disagree on pin connections.
Circuit1 instance sky130_fd_pr__pfet_g5v0d10v5_QC2ZLWxm3/sky130_fd_pr__pfet_g5v0d10v50 pin sky130_fd_pr__pfet_g5v0d10v5_QC2ZLWxm3/sky130_fd_pr__pfet_g5v0d10v50/2 connections are no connects (1322479712)
Circuit2 instance sky130_fd_pr__pfet_g5v0d10v5M7 pin VBP connections are tied together (0)
Parallelized instances disagree on pin connections.
Circuit1 instance sky130_fd_pr__pfet_g5v0d10v5_QC2ZLWxm3/sky130_fd_pr__pfet_g5v0d10v50 pin sky130_fd_pr__pfet_g5v0d10v5_QF5B2Dxm2/sky130_fd_pr__pfet_g5v0d10v50/1 connections are no connects (1322408352)
Circuit2 instance sky130_fd_pr__pfet_g5v0d10v5M7 pin VDD connections are tied together (0)
Parallelized instances disagree on pin connections.
Weston Braun
06/14/2021, 1:33 AM