set the channel description: Modems, DSP, PHYs, MACs

Hi Rob, what abou making stuff for telemetry, like Spread Spectrum?

@User oh like super low bandwidth stuff?

Yes, LoRa like

CDMA is pretty easy and straight forward to demod, also lessens the burden on developing a high performance RF front end

802.11b uses DSSS, and basically here's the demodulator: https://github.com/Nuand/bladeRF-wiphy/blob/main/fpga/vhdl/wlan_dsss_despreader.vhd

Thank You Rob, I will take look at the design

Hi @User

I didn't know that BladeRF is opensource

Good to know.

Big fan.

But I see you are implementing it on Altera FPGA

Which is I believe 14nm or 22nm if I remember correctly

Which FPGA your are using?

not exactly sure but I think the Cyclone 4 + 5 are 65nm

Hello everyone. Recently we published this paper https://ieeexplore.ieee.org/document/9433678 about our work with reconfigurable Modem. We tested it using FPGA and minimum analog stuff as shown on paper. Next move will be synthesize using openlane (actually I tested using ghdl plugin to convert VHDL core in verilog before running openlane) and design the analog integrated parts to work together.

Who is playing Base in this Band?

we’ve replaced the bassist with a square wave generator thats why this channel is dead 😞

I can't see the history of the channel. But was it about Wireless baseband processing HW? programmable?

If memory serves, yeah. We don't pay for this Slack space... frankly I think Slack may have been a bad pick for this given that it's more of a community forum than a workspace

@User has left the channel

Hey folks, forgive me if this is the wrong place for a question like this. This is probably a stupid question, but how much of an effect does a process node have on whether it's possible to implement a high-speed PHY/SerDes? For example, is it possible to implement PCIe 5 on a 130 nm process? If not, what exactly gets in the way?

@Andrew Hodges It comes down to the speed required for the SerDes and that fundamentally comes down to the gm/C the process can provide. Higher gm/C means you can go faster - you can charge capacitance faster and therefore change the voltage. Larger nodes have higher capacitances (C) both directly in gate area and parasitics. You can buy gm with power consumption, you can burn more current to make things faster but that ends after a point too. Once you get to the transition frequency of the transistor there's not much you can do. It would be very difficult to make PCIe 5 on a bulk silicon 130nm like skywater 130nm (note that stating a node size is not sufficient, if you have FD-SOI slicon or SiGe process the litho size can be the same but performance very different). Is it impossible? Could someone trying very hard with very good modelling tools and willing to spend a huge amount of current and area on inductive resonances just be able to squeak through an implementation? I don't know. But it would be highly impractical

@yrrapt thanks! what does gm mean?

gm is the tranconductance, how much current passes through the FET based on the voltage applied between it's gate and source. That's based on a small signal model (in saturation), the large signal model is more complicated but the general idea is the same

@Nathan Olson has left the channel

@Andrew Hodges has left the channel