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awesome open source ASIC resources - pull requests welcome! https://github.com/mattvenn/awesome-opensource-asic-resources

@User you have some weird setting in your filesystem, may be there is another installation done with a different user, or something else... Anyway, try to delete these two directories:

rm -rf ~/share/xschem

rm -rf ~/share/doc/xschem

and redo

make install

.

@User a PDK_ROOT environment variable is optional and tells xschem(and other EDA tools) where the skywater stuff is installed. If this variable is not set xschem does some guesses (in home dir, and /usr/local) and if it finds a valid install it will use that one. The message you get about missing PDK_ROOT is just a warning, not an error. Another suggestion, do not launch xschem in the background (

xschem &

), use

xschem -b &

. Xschem uses the terminal as a command shell, the -b option tells xschem to detach from the terminal and then you can launch it in the background.

People here might also find Tim Edwards older presentation at https://isn.ucsd.edu/courses/beng207/lectures/Tim_Edwards_2021_slides.pdf

Hello all, I was trying to find information about chips in SKY130 related to power management applications such as DCDC converters for energy harvesting. I didn't find much of this among the chips submitted until now, I guess other factors come to play here such as device robustness and current driving capabilities. I noted there are some 20V transistors, did anyone try them? would they be useful for such applications, e.g. boost converters? does anyone here have good examples or can guide me in the first steps?

UPDATE: Note to myself to never call my variables time, yet why did it convert my waveforms to discrete I was using .meas command with ngspice and as soon as I run that command, I am not able to view my waveforms(actually I can plot them but they turn into discrete values, instead of a regular analog waveform) Not sure what's up. Has anyone ever used the above in spice?

Next VSD-HDP Free webinar - High speed VCO design/Tapeout using SKY130 It gives me so much immense pleasure to present you another VSD-HDP success story - A Free Webinar on "*A High Speed VCO design and Tapeout in Skywater 130nm Technology node*" by @User . Dario joined VSD-HDP like 3-months back, and we still remember him saying that "when he was looking for special VLSI programs on analog design on google, VSD-HDP program topped up at search engine". Now I am not sure how, as VSD doesn't spend on SEO at all. I believe it's because of your word-of-mouth promotions that we topped the list. Really Thankful to every audience reading this and leading us to Dario. That's how VSD quality IP/SoC design program has made its way to the top Here are the FREE webinar registration details Date/Timings - 12th April, 8pm to 9pm IST Registration link - https://www.vlsisystemdesign.com/vsd-intern-free-webinar/ About Speaker - Dario is an Analog/Mixed Signal Design Engineer with experience in low power audio circuits. He has successfully taped-out a number of chips into mass production for high end smartphones which have sold millions of units. He holds a patent for a novel frequency divider architecture for use in PLLs and other circuits. His broad range of interests have led him to explore various areas of knowledge from analog design to machine learning to fine arts. About Mentor - Dr G S Javed obtained his M.S. and Ph.D. from the Indian Institute of Science, Bangalore in 2016 for his work on low power integrated instrumentation circuits for sensing applications. From 2016 to 2020, he led and managed a 15 member transceiver design team in Terminus Circuits. He worked on high-speed wireline transceivers (upto 20 Gbps) focusing on the Receiver design, high speed RO and LC PLLs (upto 16 GHz), and CT Sigma Delta ADCs. From August 2008 to July 2010, he worked as Deputy Engineer with Integrated Circuit Design Center(ICDC), Bharat Electronics Limited (BEL).He enjoys photography, travel and meeting people. We are really excited to share our 10-week VSD-HDP experience with all of you. See you at webinar

We are all set for tonight FREE webinar on "High Speed VCO Design and Tape out in Skywater 130nm Technology" Registration will close in 4hrs. If you have registered, you must have received meeting invite already. If you haven't here's the link https://www.vlsisystemdesign.com/vsd-intern-free-webinar/ All the best and see you in 7-hours from now

@User Thanks for the suggestions again. But in case of the step " redo make install " i had to again do "sudo mak install" as it was showing make erros in the former case. @User I watched a video tutorial of plotiing VTC of an inverter on by you where you are using "madvsi" library of the models which contained tt_models, sf_models, ss_models, fs_models etc. I copied the directory "madvlsi" into "/home/rahul123/share/xschem/xschem_library/" and now when I lauch xschem (using xschem -b & ) from either home or from "~/.xschem/xschem_library/xschem_sky130/" , there are two libraries for inserting the symbols, to create a schematic, which are " devices" and "madvlsi". I followed the instructions as demostrated in the video (the link is pasted below) but as shown in the video when I click on the button "netlist" it creates a netlist in the directory "~/.xschem/simulations". But when i try to open the netlist from the xschem window it does not open. In the menu bar of xschem, there is a menu "simulation" ---> "edit netlist" but it is not popping out the netlist. It is neither simulating the design as shown in the video nor showing the resulting waveforms. Please help me to deal with this situation. I am stuck in between. Thanks & Regards Rahul.

@User if Edit netlist menu is not working check out the

editor

and

terminal

variables in xschemrc. My suggestion is to install on your system gvim and xterm. You can change these variables to use different editors and terminal windows, but in my experience desktop environments (Kde, Gnome, others) have buggy terminal window implementations, so i suggest using xterm or rxvt / rxvt-unicode.

My first design is coming up rather nicely :) An LC tank for a 60GHz VCO. I did PLS on the tank (asitic for the coil, magic PEX for the varactors) and it's starting to take shape! Still to do: cross-coupled pair, coil guard ring, output buffers.

Hi @User Did you EM the design?

If yes, which tool did you use?

hello all, My ngspice simulations are crashing due to maximum data size reached, please see the attached screenshot. Does anyone know how to increase this max size?

Hi Everyone, I’ve been working on a guide to install the analogue tools from a clean Ubuntu/Debian machine. I used your Makefile @User as a template - so thank you! I’ve got the actual installation guide in a very rough raw html form, and I’m currently working on a ‘my first design’ pipe-cleaning exercise. I’d really appreciate it if people took a look and suggested any improvements I could make or additional tools to install (digital tools are on my list). Also if people would like to follow the guide, let me know if you come across any issues that lead you to have to type anything other than what is in the guide so I can make it more comprehensive. It’s available here: anthonywall.ie/opentools @User let me know if you want to collaborate or take some of this info for the SSCS page

I am lost in the PDK. Where do I find the layout of the bipolar devices e.g. pnp and npn ?

It's been a long time since I shared any updates about Mosaic here. I just uploaded a short video where I draw and simulate a simple opamp. There are still a lot of bugs to fix and features to add, but it's starting to be realistically possible to design circuits with it. There will be some major changes before V1.0 but as always, any feedback is greatly appreciated.

Hello all, I'm trying to understand the 20V devices available in SKY130. From the documentation at readthedocs, the current driving parameters seems to be the ones pasted below. What's the difference between these 3 currents? did anyone design with the 20V devices already? And, in general, how can we check the meaning of the model output parameters in the tables?

Hello all, I'm trying to obtain a transient vintage berween gate and source of a transistor (and, more generally, a voltage difference berween two nodes) in ngspice but i can't fine good examples, I tried the VCVS idea proposed in the manual and the .probe statement on the device berween g and s nodes, but the result doesn't appear at the output, does anyone have a working example?

@User the general format for getting the voltage difference in ngspice plotting facility is to do a '`plot v(gate,source)`'. Doing

plot gate-source

yields the same result.

@User Also xschem can now directly display ngspice simulation data, even expressions between saved variables. Just use the RPN notation (RPN is way simpler to parse 🙂 )

Have there been any projects that verified transistor noise in anyway?

60 GHz VCO, still ongoing 🙂 • Done (more or less): ◦ CCP ◦ Varactor banks ◦ Inductor plus guard ring ◦ Buffer fet connections • To do: ◦ Buffer loads (microstrips) ◦ CCP current mirror ◦ RF pads ◦ Biasing, biasing everywhere! ◦ Figure out about the placement of density tiling inside the top cell (HALP!) Simulations tells me that it oscillates at around 60GHz with a FTR of 4.5% (taking into account most of the parasitic loading sans inductances)

People might find this paper interesting -> https://www.researchgate.net/publication/354364068_Fifty_Nifty_Variations_of_Two-Transistor_Circuits_A_tribute_to_the_versatility_of_MOSFETs -- Would love to see all of them done on SKY130!

Hail Hydra The basic VCO floorplan is quite done, me thinks. For now I have about 430 um x 340 um of surface. I have completed the layout of all the major blocks of the circuit, which are:

CCP

Biasing current mirror

Buffer mosfets, load and impedance-matching

Differential varactor banks

Inductor plus guard ring

Now I have to re-extract parasitics on the top cell connections (plus parasitics on the current mirror, which haven't been extracted yet ^^' ) and start worrying about the chipathon project submission - and to upload it to github 🙂 PS: the RF pad is merely a placeholder. I feel like it deserves a bit more care - the parasitics are too large, I'm afraid.

@User older than that. It predates the standard BSD licensed terms!

Hi all! I am looking for interns and / or postdoc with experience in both analog and / or digital design. Please reach out to me at: mehdi@umich.edu

Hi everyone, I've been around for a while, but this is my first message, so just let me briefly express gratitude to all contributors that have enabled this, one of the greatest, moment in technology history. Now, on the topic - I am experiencing a strange slow-down with NGspice loading SKY130 libraries... It takes close to a whole minute (yes, 60 seconds) to load and simulate a CMOS inverter... Has anyone experienced anything similar? I'd be happy to provide more information, netlist, env and other, but for now just wandering if this is something that is supposed to happen, or is something wrong with my setup...