Ok. I will try that tomorrow

why do you load the .gds file instead of the .mag file? I think the .mag file allows you to set the port ordering while importing a gds file has no such guarantee?

I do my layout in KLayout which uses GDS as it's file format. Then I load it into magic for DRC/LVS/PEX

@User, I have some "half layouts" in my design which get mirrored and in some cases it's ideal to have e.g. vie cell instances on the mirror line which will result in those cells exactly overlapping at the top level on the axis of symmetry. Will this cause a problem when the design goes through the thorough checking phase or can I assume it's ok it it doesn't violate magic's DRC rules?

Oh, I see. Its adding more port connections to the module that is not my top level module.

should I flatten my design before extraction?

@User: For full R-C extraction, it is probably a better strategy for now to flatten. The original extresist code was written only for flattened circuits, and while I have done a lot of work to get it to work hierarchically, any errors stemming from "extresist" are most likely coming from those efforts to preserve hierarchy.

Also, it seems that some part in the process is not preserving the port order. In particular, it seems to be putting the 0th port as the last port in the spice subcircuit

it goes 1st - nth, 0th

Note that "extresist" uses the ".sim" format as an intermediate form to save nodes and connectivity, and since ".sim" is a flat format, there is a definite disconnect that is being worked around in convoluted ways.

It is a good time for me to be debugging the extraction code, though. I wanted to get two major things done before the 2nd MPW, which was correct substrate extraction for deep nwell circuits, and correct hierarchical R-C extraction. I got both about halfway there. . .

Also, (I think its at this step) when I flatten my netlist is says there are warnings but does not print them. Any way to check the warnings?

Extracting opa_flat into opa_flat.ext:
opa_flat: 6 warnings
Total of 6 warnings.

<!channel>: Announcing (finally!) the availability of the caravan analog and mixed-signal harness chip and the caravel_user_project_analog repository, where you can download the wrapper for analog user projects. The user project system works in the same way as the standard user project wrapper, with essentially the same instructions for submission and running pre-check through efabless. See the repository for more information: Caravel analog user project repository . And flag me down in this channel if you have any questions, concerns, or needs. Thanks for your patience!

Thanks @User. I thought the

caravel_user_project_analog

was supposed to use a

caravan

submodule though? But it seems to use

caravEL

. Is has something changed?

the extraction seems to be generating floating nodes due to the connection of the extracted capacitances. This causes issues with ngspice. Is there any way to prevent floating nodes / automatically add some large resistance to ground?

I see the manpage for ext2spice says:

−F
Don't output nodes that aren't connected to fets (floating nodes). Normally capacitance from these nodes is output with the comment **FLOATING attached on the same line.

Is there any other recommended way of doing it? It would seem that just not outputting the capacitances with a floating intermediate node leads to less accurate extraction

@User: Try the RSHUNT method, and if that isn't solving the problem, I'll be looking into proper solutions.

That works. Thanks!

One question on the operation of all the extraction tools (the manpage does not seem to be very detailed, unless there is info somewhere else?): The commands seem to have state, where all the examples I am seeing call ext2spice and other commands multiple times with different arguments. What is going on with each run?

rshunt works, but I tried removing the floating capacitances with the -F flag on the last call to ext2spice and it did not work. I assume I would have needed to pass that flag in on one of the earlier calls or something.

@User I am getting results that can not be correct when simulating the RC extraction netlist (but it does seem to be simulating). I am getting some weird error messages. The first is that it can not open .sim files for my some submodules, even though I have flattened the design.

exttosim finished.
Cannot open file cascode_bias.sim
Cannot open file folded_cascode_p_in.sim

The second is that it is flagging a single poly contact as being too small to extract despite it being no different than all other gate contacts on the generated FETs

Warning: polycont at 13893 -3555 smaller than extract section allows

It is also complaining about missing SD connections, but I think that is just due to dummy / series fets or something?

missing SD connection

@User: The contact issue is a known issue with stacked contacts; it should have a minimal impact on the extraction (and I'll get around to fixing it, eventually). The "missing SD connection" is the usual complaint about tied source/drain and should not be causing an error. Why it's looking for subcircuit .sim files in a flattened layout, I have no idea.

Right now I am running this on a layout that has one sub-cell:

load folded_cascode_p_in.mag
box 0 0 0 0
flatten folded_cascode_p_in_extracted
load folded_cascode_p_in_extracted
box 0 0 0 0 
port ibias index 1
port in_m index 2 
port in_p index 3
port out index 4
port vdd index 5
port vss index 6

extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0.01
ext2spice extresist on
ext2spice

just extracting capacitance gives results that match the schematic simulation well. Trying to extract resistances with this puts my gain at -240dB instead of 40dB, so something seems to be horribly wrong with the connectivity of the generated netlist or something.

https://github.com/ALIGN-analoglayout/ALIGN-public has anyone used this for converting xschem schematic to layout?

Is There other know better way to convert schematic to layout automatically?

@User: Analog place and route is a hundred times more complicated than digital place and route. There are systems like #fasoc and #bag that approach this in different ways, but the usual approach is schematic-driven layout, not automatic layout generation from schematic.

@User i would take a look at https://github.com/magical-eda/MAGICAL

In

sky130_fd_pr__res_xhigh_po_0p35

does the

rend

resistor account for the resistance of both contacts? I want to make sure I'm reading this right.

Hello! I want to perform a transient noise simulation, the ngspice documentation establish that I have to use a

vsrc

configured with a

trnoise

functionality. Will this also turn on the noise in the transistors? or it only simulates the noise in the voltage source? Has anybody tried simulating something like this?