To everyone: I just updated the PDK Tcl scripts in magic to add an option on all devices to take the contacts up through via to metal1. This is particularly important for the SkyWater process since the local interconnect layer is fairly high resistance; you don't want to do any routing on local interconnect. Changes were pushed to the open_pdks repository master branch on opencircuitdesign.com and will be mirrored to the github site overnight.

Hi @User!

Ah yeah, I had noticed it was doing some long routing on there between macros and I added an obstructions to stop it from doing that.

@User Does this kit support Inductors? I can see inductor 1,2 & 3 under devices 1 in magic.

@User: Inductors would best be done on the redistribution layer, but we have no plans for that for this tapeout, and everything is running late enough that I will probably work on the post-processing layout after tape-in. The inductors under the "Devices 1" menu are broken; the final devices that we were able to pull from the SkyWater libraries are on Metal 3 and look like they belong to an older variant of the process (no longer supported) that had three layers of metal with a thick metal3. It is well worth scaling those up a bit and recasting them to Metal 5 and characterizing them. The main problem will be the effect of having large bump bonds on top of the whole layout.

@User: The devices I referred to are in sky130_fd_pr and are called "rf_test_coil1" through "rf_test_coil3". They have a weird pizza-slice pattern drawn on top in the LVS text layer which I don't know the reason for. Otherwise, they look like typical octagonal coils. Probably it would be best to give up on those, and make a parameterized cell that automatically generates coil designs, then fill a test chip with them, and figure out how to map the coil parameters to the measured inductance.

Ever wondered what 1st Year Master student can do in area of Analog IP design with zero experience? Very happy to announce the first PLL IP built from scratch using Sky130 PDK's by @User under 8-week VSD Research IP design Internship program Here's the GitHub repository: https://github.com/lakshmi-sathi/avsdpll_1v8 The whole 8-week journey of building this IP is actually a story worth listening to, and may be we will tell that at our felicitation program Bottom line, if anyone is interested to build SoC around PLL (we are also doing it parallely), you are most welcome to join and contribute The good thing about this IP is its completely open-sourced till GDS level, so you can download, simulate and look at its characteristics Future work involves characterizing same IP across all corners and make it a robust one

Hi @here

We are happy to announce that we have created a script that installs all the tools necessary for starting with Skywaters 130

It's mainly focused on Analog Design and RF.

@User You might want to look at this as well https://www.udemy.com/course/vsd-a-complete-guide-to-install-openlane-and-sky130nm-pdk/

Really nice

The idea of the script to make the life of a person starting easy.

@User I don't have bias current. I set the Vbiasn at 10uA. But I couldn't get the current Vdmy3 on graph when i plot on ngspice. Similarly for the Vdmy2 on graph. Vdmy2 and Vdmy3 has 0 Voltage sources for plot on ngspice.

@User first set the dc operating of the circuit. comment all .ac, .dc, .tran, insert just a .op, then after simulation do a 'print all' to verify your operating point. If all is ok then insert an AC signal somewhere (depending on what you want to do) basically "vxxx node1 node2 AC 1 0" and run .ac analysis. Values you see in AC analysis are small signal deviations (more precisely it's the circuit behavior linearized in the operating point), amplitude and phase w.r.t the ac source, in the frequency domain. Normally you set the ac source with amplitude 1 and phase 0 so any value you read from circuit voltages is the transfer function (Vo/Vxxx). If no ac source is set all values are zero in the circuit during AC analysis since there is no deviation w.r.t. the dc point.

@User: You did an AC analysis an plotted current vs. frequency. Vdmy3 is measuring a DC current. The AC component would always be zero, so the graph you get is what you should expect, it is not?

Hi everybody! I'm working on an opamp, i have succesfully simulated my desing in xscshem and now i'm working on the layout. I have a doubt with the integration of my desing in the caravel top level. All my inputs and outputs are analog singal, and i would like to know how to connect them to the pads without any digital interface. Is there any example of a user project integration in caravel layout? Thanks in advance.

@User: There is no example of a project using analog. However, the general rule is: Connect to any GPIO pad above GPIO[7] (the ones from 0 to 7 will be connected to other chips on the development board). Connect to the pins in the user project wrapper cell called "analog_io". The management SoC must then execute a program on startup that turns off all digital signals on the GPIOs where you are using analog signals. There is one "analog_io" signal per GPIO pin. Bear in mind that the analog_io pin connects directly to the pad (through a small resistor).

Hi everyone! hope you're great. I'm working on a mixed signal design to be integrated in the caravel chip. I'm in a little problem with the mapping of the pins. There's a video where it's shown how to use the user_project_wrapper_empty.gds. It's said that one have to stick the design to that space and that pin location, and at the end of the design, running the make file, the mapping of the pins of the design with the pins of the gpio interface is automatically done. My problem is that in the user_project_wrapper_empty.gds there are only 3 pins related to a single gpio interface (i.e. io_oeb[9], io_in[9] and io_out[9] related to the gpio number 9) but in the documentation (https://skywater-pdk.readthedocs.io/en/latest/contents/libraries/sky130_fd_io/docs/user_guide.html) and in the gpio layout there are 26 possible connections. Where do i have to specify the one i want to use? As an example of what i'm trying to do, i attach an image. I need to link the io_in[9] in the subfigure 1, to the pad_a_noesd_h pin of the gpio in subfigure 2 and 3.

image.png

Thanks in advance!!

You don't choose. In the latest version of the caravel there is a 4th pin per gio

analog_io[9]

It is however not the

noesd

one. AFAIK there is a small resistor between the pad and that connection.

@User (@User): I did not want to have users connect to the ESD-sensitive pin by default. If you must connect to it for some reason, you should be able to route out to it. If not, let me know.

Hello @User, we actually need to use the pad_a_noesd_h pin, please can you tell us how do we have to proceed? Can we manually connect them in magic? or is there any configuration file we should modify? Thank you for your help!!

@User: Yes, I think you can just make the connection in magic directly to the pad. If there is any problem with that, then let me know.

Has anyone integrated an analogue design into Caravel yet? There are still some open questions I have. I have started listing the things I believe to be true and things I see as blockers here: https://github.com/yrrapt/amsat_txrx_ic-caravel/blob/master/analogue_integration.md I will happily accept pull requests or just manually change things myself if anyone has any corrections/improvements