layout

leaisnotr1

@User Thanks!

anyone using ASCO for model optimization?

Hi @here, Does anyone knows what are the requirements for getting our design in the shuttle for analog designs?

The general requirements are (and @User will need to correct me if I have any of this wrong) that you will need to have at least GDS of your project and have it up in a public repository like github; you will want to fork the efabless/caravel project from github and replace the example project in it with your user project. The github repository for caravel does not yet have the layout; we are still running a few passes through openlane. If you can keep your project within about 2.8 x 2.8mm, it should be okay; I believe we are on target to get closer to the 10mm^2 we promised, which is more like 2.8 x 3.2 or maybe a little taller.

The efabless submission site will have you list the URL for your repository, and will grab the contents automatically. We will provide you with a script or set of scripts to run basic checks (DRC, density, etc.) which should ensure that the design meets requirements (as best as we can check them with the open source tools).

Sounds Great

Thanks @User

how do I include a finalized analog cell in the verilog when integrating to caravel? this might be an #openlane question more than here..

Hello everyone

We are working on improving the SKY 130 PDK documentation. What kind of plots/diagrams generated from the library cells would be usefull for you?

I've got some code which generates gm/id plots for the fd_pr primitives. It would be useful to get these into the pdk docs.

@User: Please see the git repo https://github.com/dentistformyeye/rule-diagrams ; This is the work of one of my summer interns, to automatically generate SVG diagrams of DRC rules from the CSV files of the rulesets. Hopefully it can be of some use to you. I would like to see the "diagram.py" code refined and extended. It is preferred to have the DRC rules in SVG format, and preferred to have one illustration per rule, rather than the big mess that is the SkyWater DRC illustrations, with many rules in one figure, all scattered around, and with some rules missing, some not correct, and many where the text obscures what's being illustrated.

@User that's a nice tool.

Also makes me think of the DRC unit tests that was discussed a while ago. Once that tool is up and running it doesn't seem a huge step to then generate GDSs which are just over the pass/fail criteria

@User This isn't really a diagram/plot but I would love to see some offset information, especially since the monte-carlo isn't up and running yet. Some pelgrom values would be super useful

@User: You should tell that to my intern, not me. He's a high school student, by the way. . . I live near a high school with a very good science and math program. So I took advantage of that talent to get myself a few interns for the summer.

@User: Yes, I agree, extending it to generate both SVG and GDS (or I would prefer magic) should be rather easy.

Given that the pad_a_noesd_h connections go through ESD protection, if the supply pins were left floating, would that allow the use of higher voltages at the user pads?

@User: How high a voltage are you looking for? The caravel chip does not have any straight-through (i.e., simple analog) pins; there are either the power domain pins or else they are GPIO and connected to digital circuitry. You can apply up to 5.5V on the VDDA power supply. Above that, the user domain VDDA2 pad might be able to go higher, but it's still connected to a high voltage clamp circuit as well as the pad diodes, so you would want to check whether anything would be overloaded. But it depends very much on just what voltage you're planning to apply to it.

From another thread, I think the question is motivated by trying out the SONOS devices.

I'm personally working on a scope frontend (basically some opamps) design using those 10v5d5v0g devices that I hope I can run at 10v.

I think there would be interest in an analogue version of caravel with most pins straight through and people can add ESD if they want.

I'm slightly concerned all the MPW submission stuff assumes everyone wants to go RTL to finished chip. In my impression of the discussion here, that's not very representative of what the community is working on at all

@User around +7V and -5V for the SONOS devices. They will be in a deep n-well if that makes a difference.

@User: Go ahead and assume that you use VDDA2 = 7V and VSSA2 = -5V. The power supply pads on the padframe will need to be decoupled from the voltage clamps; we can swap in the appropriate padframe layout if you have the correct alternative pads and connections in the top-level verilog. Use the power pad from sky130_fd_io without the overlay and without making connections to the clamp in that cell, and you should have a simple direct connection between core and pad. But I think that configuration still has pad diodes, which would not work with either voltage; especially the -5V will clearly forward-bias the pad diode to VSSIO, and I don't think +7V is going to be okay on the VDDIO diodes, either. I'm sure a solution is doable, I'll just have to investigate how to break down one of the power pads into simpler subcircuits that don't have the diodes or clamps.

@User: This is all in keeping with the original plan to have some set of pads on the padframe swappable by the end-user. I just have no formal method for that, and for this tapeout it will be done on an as-needed basis.

We could use opinions on how to best show things in https://github.com/google/skywater-pdk/pull/237

I'm putting together a jupyter notebook to assist with gm/id sizing. Someone want to take a look and provide feedback?