How Freshers & Pros Are Accelerating Their VLSI Careers with #cloud #based Semiconductor Fabless Accelerator Lab (SFAL)- VLSI System Design (VSD) #VLSI #SoC Design program using Synopsys Inc EDA Tools (#EDA on #Cloud) Reg link - https://www.vlsisystemdesign.com/sfal/ The semiconductor industry thrives on engineers who can navigate the end-to-end SoC design flow—from RTL to GDSII. But how do you bridge the gap between theory and real-world expertise? The SFAL-VSD program offers a structured 12-week journey to master Synopsys EDA tools while tackling industry-grade projects. Here’s what makes it unique: 1) #Phased #Learning: a) Weeks 1–6: Build fundamentals in floorplanning, CTS, routing, and verification. b) Weeks 7–10: Specialize in advanced topics (low-power design, timing closure) and work on a capstone project mirroring real-world tapeouts. c) Weeks 11–12: Polish professional skills like GitHub documentation and interview readiness. 2) #Industry-#Aligned #Projects: a) Design and tapeout an entire #C0169AR1RL6 based SoC using #SCL180nm or #SKY130nm PDKs using industry grade EDA Tools on #cloud 3) #Expert #Guidance: a) Learn from professionals with decades of experience. One alumnus shared: “The capstone project gave me a portfolio piece that impressed my current employer.” #Why #Join #SFAL-#VSD SoC design program? 1) Freshers: Turn academic concepts into job-ready skills. 2) Professionals: Upskill with specialization in high-demand areas. 3) All Graduates: Walk away with a polished portfolio and industry connections. 4) Ready to accelerate your VLSI career? Explore the SFAL program here: https://www.vlsisystemdesign.com/sfal/ The future of chip design demands skilled engineers. Are you ready to lead it?

hello, im playying with xschem and ihp openpdk and i cant run simulation. Plot window wont open, netspice command bar neither. Here is xschem project file. Can you help please?

can the specification of the current-density in the metal-layers be exceeded it one dont need the maximum temperatur or can accept shorter life-time of the chip?

Here's a simple, functional RISC-V processor and SoC implemented in Verilog and FPGA proven (for learning RISC-V and building cool applications) https://github.com/vsdip/vsdfpga_labs The provided RISC-V core and SoC are *perfect for beginners*—clean, minimal, and easy to grasp. Here’s what makes it special: • Core Features: ◦ Implements 10 essential RISC-V instructions (ALU ops, branches, jumps, load/store, etc.). ◦ Handles all 5 immediate formats (U, I, S, B, J) for instruction decoding. ◦ Simplified 5-stage state machine (fetch, decode, execute, memory, writeback). ◦ Memory-mapped I/O for peripherals (LEDs, UART) and a 6KB RAM. • SoC Integration: ◦ UART communication for serial output. ◦ GPIO control for LEDs. ◦ Clock/reset management and FPGA-friendly design. This code avoids "black box" complexity—every component is transparent, letting you see how instructions execute cycle-by-cycle. Whether you’re simulating the core, modifying the ALU, or adding new instructions, the minimalistic structure ensures clarity. Educators can leverage this to teach digital design, RISC-V architecture, or embedded systems, while students can build real projects like UART-driven apps or LED controllers. P.S. Share this resource with colleagues—turn theoretical knowledge into tangible innovation.

Something truly extraordinary happened today - a glimpse into the future of India’s Semiconductor Mission! Kids from 6th and 7th standard are already diving into VLSI design using the VSDSquadron FPGA boards. Today, they interfaced tilt sensors to detect motion - a hands-on application of concepts that once belonged only to advanced labs! This isn’t just a milestone. It’s a movement. India’s Semiconductor Mission just got real - and it’s in incredibly safe hands. Here’s a short video that proves how far we’ve come. The future is not just bright - it’s already here. Link to FPGA board and the internship program - https://www.vlsisystemdesign.com/vsdsquadronfm/

A fun opportunity for ASIC enthusiasts this summer! Details: https://www.redwoodeda.com/showdown-info

Would anyone in the mountain view office like a free reflow oven?

12" wide, 11" deep, and 7" tall

Let me know by EOD today

Yes I am interested

Can pick up

Let me know @Tom

Im in palo alto

@James Stine I thought I was messaging my work slack but if you're in mountain view or San Jose you can have it

Oh perfect. No problem

Great

Thank you!!

Can you collect it from me?

Yes

Let's move to a private chat

My brother will pick up - just let me know details

Thank you again!

If you're aiming to design custom chips and boards like the Caravel Chip (VexRISC-V, USB programming, 38 GPIO, 4Mb Flash), you have next 6-hours to enrol in Digital VLSI SoC Design Workshop that exactly does the job. It focuses on RTL-to-GDSII workflows, open-source RISC-V integration, and system-level planning - skills critical for IoT, robotics, and automation projects. https://www.vlsisystemdesign.com/digital-vlsi-soc-design-and-planning/ The workshop prioritizes technical execution (10%) and project management (90%) - the dual engines of real-world success. Enroll to secure lifetime access to the VSDSquadron board and start building. If you are interested to access the blue board with lifetime access to VSD RTL2GDSII lab content videos, here's the link - https://www.vlsisystemdesign.com/vsdsquadron/

Opensource silicon is back. Great job 👏 @mikewishart @kassemmkk @mkk https://chipfoundry.io/

Hi i am having some trouble simulating the dc_**v_**mos.sch files in the ihp testcases. Does anyone have a clue of what i might be doing wrong? Thank you

Hi open-source silicon world! 👋 My startup is looking to hire someone to design a mixed signal test chip for an embedded system capable of ultra-dense physical sensing and compute—well beyond anything currently available. This is a paid consulting opportunity. (Note: the design would be for a more advanced node than SKY130.) If you’re interested or know someone who might be, please DM me. Would love to connect! 🚀

Hello my Brothers and Sisters in Sillicon! Do any of you have any experience with DFTs? Specifically with TPI?

Dear all here goes the repository you can PR your designs. We will close the submission 9-th of May. https://github.com/IHP-GmbH/TO_May2025

The Strategic Evolution of VSD RISC-V/FPGA Development Boards: Why We Built What We Built The RISC-V and VLSI communities are rewriting the rules of computing, but innovation requires more than ideas—it demands tools that bridge ambition and execution. At VSD, we’ve spent three years crafting a lineage of development boards to solve critical gaps in this ecosystem. Here’s why each board exists and how they empower engineers, educators, and startups: 1. VSDSquadron Main (2023) Born from a glaring need in academia, the Main board became the first platform to merge industrial-grade VLSI workflows (RTL-to-GDSII) with hands-on RISC-V programming. With a 100MHz VexRISC-V core and 38 GPIOs, it gave students a sandbox to validate both chip design and embedded software—a rarity in curricula dominated by theory. But as RISC-V adoption grew, developers demanded affordability, not just academia-grade rigor. 2. VSDSquadron Mini (2024) The Mini answered the call for accessibility. By stripping down to essentials—24MHz core, 15 I/Os, and 10-bit ADC—we cut costs by 60%, making RISC-V development viable for hobbyists and startups. Its simplicity became its strength: a gateway for IoT prototypes and edge devices. Yet, as commercial projects scaled, the need for enterprise-grade performance became undeniable. 3. <https://www.vlsisystemdesign.com/vsdsquadronPro/?awt_a=5L_6&awt_l=Dd2JQ&awt_m=3kQG4Y9L8wA8._6|VSDSquadron PRO (2024)>* The PRO board marked our pivot to industrial adoption. With SiFive’s 320MHz FE310-G002, USB-C, and Quad-SPI Flash, it delivers the throughput and reliability needed for robotics, automation, and high-performance computing. This wasn’t just about speed—it was about aligning RISC-V with legacy ecosystems while retaining open-source flexibility. 4. VSDSquadron FPGA Mini (2025) FPGAs are the unsung heroes of VLSI validation, but proprietary toolchains and costs stifle innovation. Our FPGA Mini disrupts this with 5K LUTs, open-source workflows, and 39 configurable I/Os—a 70% cost reduction over traditional solutions. It’s not just an FPGA board; it’s a statement that ASIC prototyping should be accessible to all. We didn’t just build boards—we built stepping stones. The Main teaches, the Mini lowers barriers, the PRO competes with legacy architectures, and the FPGA Mini dismantles proprietary walls. To the Engineers and Educators Shaping Tomorrow Your feedback drove this evolution. When academia needed rigor, you spoke. When startups needed simplicity, you demanded it. Now, as RISC-V reshapes industries, we’re committed to delivering tools that keep pace with your ambition. So What’s next? WiFi/BLE, AI/ML acceleration, security co-processors, and tighter cloud integration - all guided by your needs. The future of open computing isn’t just about instruction sets; it’s about enabling your ideas without compromise.

You are either building cores or depending on those who do. The RISC-V based MYTH Workshop is where you move beyond concepts and actually build a modular, pipelined RISC-V processor from scratch. https://www.vlsisystemdesign.com/riscv-based-myth/ Instruction fetch, decode, ALU design, memory handling, control flow - every critical block, connected the way real CPUs are built. This is not a simulation exercise. This is how real engineers are made. The final cohort of the quarter closes in the next 24 hours. If you are serious about mastering processor design, now is the time to act. Learn and build here