Did ChipFoundry get the open source silicon slack?

Where might be the right place to ask question about ChipFoundry harnesses - in particular the OpenFrame harness?

any idea on this information , i am unable to find the pdk they released

This was a talk show with famous tech YouTuber ICHIKEN about Open Source Silicon movement and alternative way to maximize the biz value. Appreciated! —- The narration said “reaction body”, it is funny but reflecting “反動＋体“ which was same pronunciation to “半＋導体=semi+conductor” in Japanese, good Job! yet need more practice!

Hii everyone, I’m planning to work on a complete RTL-to-GDS project on Windows 10, but I’m not aware of any open-source tools that are compatible with this setup. Could you please suggest some tools that I can use for this project? It would be really helpful if you could also share links or official repositories for those tools. Thanks in advance!

OpenROAD RTL-to-GDS on Cloud (GitHub Codespace) The setup takes approximately 7–10 minutes to complete. If you encounter any issues, please raise an issue on the GitHub repository below: https://github.com/vsdip/vsd-pd This setup is being tested for robustness - the goal is to enable and train thousands of engineers in backend design using OpenROAD. Once setup is complete, you can follow and run the tutorials available in the official OpenROAD video series: https://theopenroadproject.org/videos/

Hey Everyone! We're introducing NativeChips.ai! the first cloud-delivered Platform-as-a-Service that takes you from idea to silicon, powered by Agentic AI. 👉 The limited-access Beta is now live! - Get early access and free platform credits - Explore our design-to-silicon workflow - Help shape the next generation of chip creation Get invited to the Beta at https://www.nativechips.ai/

Received final approval that the TR-1um GitHub repository is now open. https://github.com/OpenSUSI/TR-1um Since the original DRC cannot check a full-custom layout, such as Standard Cell development, except for PCEL use, new DRC runset development is ongoing under the tech/drc directory. Additionally, the Tutorial "How to make DRC runset for KLayout" project is also ongoing; feel free to join as always. We welcome your feedback on the DRC result and bug report as well.

I recently wrote an article about #RevolutionEDA published in semiwiki.com site: https://semiwiki.com/eda/363768-revolution-eda-a-new-eda-mindset-for-a-new-era/

[STA] Best circuit conditions to demonstrate ccS superiority over NLDM vs SPICE? Hi everyone, I am currently working on a correlation study between NLDM and CCS timing models against a Golden SPICE reference. My goal is to design a specific testbench that clearly demonstrates the limitations of NLDM while highlighting the accuracy of CCS. I want to create a scenario where the NLDM error is significant, but CCS tracks the SPICE results closely. Does anyone have any idea of a circuit topology or specific conditions that are known to "break" NLDM accuracy? I am looking for suggestions on the possible circuit with NAND gates and RC interconnect. My Current Work / Setup: PDK: ASAP 7nm(FinFET). Components: Testbench uses 2 NAND gates with RC interconnects (created the SPEF file manually for the timing analysis) Simulations: I am running simulations and golden delay calculation in SPICE (Cadence Virtuoso) and comparing them with the delay obtained from Tempus (using both NLDM and CCS.lib files). Findings so far: For circuit in which a NAND drives a RC interconnect connected to another NAND gate with a output load(the other input of the gate is connected to Non Controlling value), the delay calculated for the first stage with CCS and NLDM are coming same. Thanks!

Mabrains just released it's first Agentic EDA Design Environment to the world. Open source based and driven. Let AI build the next generation AI chips. Sky is the limit. Chipro is still in beta, Community feedback is greatly appreciated. Our more powerful flows will come soon.

In May 2023, we launched the Open Source Silicon community in Japan with just a handful of passionate volunteers. Today, our Discord community has grown to over 580 members, spanning a wide range of sectors. To cap off 2025, our year-end OSS Silicon Advent Calendar is now fully booked — a testament to the momentum and enthusiasm driving this grassroots movement. https://qiita.com/advent-calendar/2025/osssilicon

Hi guys, I am working on the OpenROAD Initiative (https://openroadinitiative.org/) to support open-source EDA tools. @Indira Iyer suggested I reach out here to get your feedback on two questions: What are the trade-offs of using open-source tools vs. commercial tools? What level of support do you expect from open-source tools (community, dedicated team, etc.)? Please reply in the thread. I really appreciate your responses! We’ll use your input to fine-tune our approach in improving usability and reducing costs for chip designers. Thanks in advance!

The industry is desperate for RISC-V and Chip Design talent. (Just look at the news from AI summit and IESA Vision Summit India). VSD is the only Indian EdTech with a proven track record of 20+ student chips taped out via Google. We are launching the March 2026 batch. If you want to hold a chip YOU designed in your hands this year, pick your lane: The Specialist (Edge AI) Deploy AI models on RISC-V hardware. 2-Week intensive. Hardware kit included. (Ideal for final-year projects). https://www.vlsisystemdesign.com/vsdsquadronpro/ The Architect (Full Chip Design) Go from RTL to GDSII in 6 weeks. Learn the flow that gets you hired at Semiconductor Companies. Hardware + Free fundamentals course included. https://www.vlsisystemdesign.com/vsdsquadron/ The Beginner (Foundation) Master Physical Design basics with OpenLANE/Sky130 in 10 days. No prior VLSI knowledge needed. https://www.vlsisystemdesign.com/digital-vlsi-soc-design-and-planning/ Inventory is live. First 50 registrations get priority support.

Hi everyone, pleased to announce that the OpenROAD Initiative will be featured in Google Summer of Code 2026 as an independent organisation. We have also created a discord for this year's edition, do hop on and say hi! Project List: https://docs.google.com/document/d/1X6xxUonxgEQ_iD5G5vFp2ZOH1vbkRSspEdYrpSf4khE/edit?usp=sharing Discord Link: https://discord.gg/axCZmUbH

Hi Folks!! I need to develop a few pcells in layout (i am on ihp130 pdk). Does anyone have any example code which I can refer to get started with? To give some context, I need it to generate nwell and substrate tap rows and multi-link resistors

Just wanted to share something inspiring — Aarohi from 6th grade is exploring semiconductor chip design this summer. It’s wonderful to see kids get early exposure to how technology really works, especially with AI shaping the future. More than anything, it builds curiosity and a creator mindset. Thought it could be a great experience for our kids to explore together this summer. https://www.vlsisystemdesign.com/chip-design-for-high-school/

Are you interested in ASIC tools and pushing the boundaries of chip design and implementation? Partcl and Hudson River Trading are launching a new open competition to build the next generation of macro placement algorithms.  Macro placement is a difficult problem in ASIC physical design: discrete geometry, global connectivity, congestion, timing, and power constraints all collide in a massive search space. Classical methods like SA and analytical placement have improved for decades, but there’s still room to push the frontier. If you care about EDA, optimization, AI systems, or just want to test your algorithm against real chip design problems - this is for you. 🏆 The Prizes • $20,000 Grand Prize • $5,000 Second Place • $4,000 Innovation Award • HRT swag for every valid submission 🧠 The Challenge Participants will develop algorithms that outperform SA and RePlAce baselines on the ICCAD04 IBM benchmark suite.The top submissions will be validated through a full OpenROAD flow on NG45 designs using real PnR metrics (WNS, TNS, Area). ⚙️ What you can build Any approach is fair game: • Reinforcement learning • GNNs / differentiable optimization • Analytical methods • Hybrid search or classical heuristics • GPU-accelerated solvers ⏱️ Runtime matters. Overlaps are disqualifying. Generalization is required. 📅 Deadline: May 21, 2026 👥 Teams up to 5 people 📜 Winning implementations must be open-sourced (MIT or Apache 2.0) 👉 Repo + full rules: https://github.com/partcleda/macro-place-challenge-2026

A major milestone for India’s semiconductor ecosystem: an indigenous RISC-V SoC built end-to-end using open-source EDA tools on SCL180 PDKs. This is a meaningful step toward lowering chip design entry barriers for Indian startups and institutes. Read the blog for more details: https://www.linkedin.com/posts/kunal-ghosh-vlsisystemdesign-com-28084836_first-opensource-risc-activity-7447539071368966144-dqcC?utm_source=share&utm_medium=member_desktop&rcm=ACoAAAeZe4ABRnXXgcvVesykjXO-9WZxOuR05PE We will make the full flow official once the required permissions are in place.

Hi

Hi everyone, I’m about to start my PhD focusing on PUF (Physical Unclonable Function)research, particularly in the analog/mixed-signal domain. I’m currently exploring different directions and would really appreciate your guidance. I’m trying to decide which type of PUF to focus on for achieving good novelty and research contribution — such as: * Weak PUF vs Strong PUF * Current Mirror-based PUF * Analog PUF architectures If anyone can suggest key reference papers, important authors, or share insights on: * Which PUF architectures are currently under-explored * Challenges in analog PUF design (e.g., noise, variability, reliability) * Promising directions for novel contributions that would be extremely helpful. Also, any advice on how to approach research in this area from scratch would be greatly appreciated. Thank you in advance!

Not to be like that, but you have a supervisor right?

From the Revolution EDA April 2026 newsletter: We have two updates to share this month: a browser-based cloud trial environment is now live, and hierarchical Layout vs Schematic (LVS) verification has been added to the platform. Cloud Trial Environment --- Revolution EDA can now be evaluated directly in a web browser, eliminating the need for local installation. The trial is available at cloud.reveda.eu:3000. To start a session, enter your email address and click the login link you receive. Each session runs for one hour. The trial environment includes schematic capture, simulation workflows, layout editing and verification, and an integrated AI terminal. Email addresses are not stored unless you opt in to receive updates. Revolution EDA is the first European cloud-based EDA platform focused on analogue and mixed-signal IC design. Hierarchical LVS Verification --- Revolution EDA now includes hierarchical Layout vs Schematic (LVS) verification. LVS confirms that a chip's physical layout matches its schematic, catching errors before fabrication. The initial implementation covers the IHP SG13G2 technology node, using IHP rule decks run through KLayout in headless mode. The tool runs directly from within the layout editor. It automatically extracts netlists, verifies device and pin connections across hierarchy levels, and produces detailed violation reports. After reviewing violations, corrections can be applied and the design re-verified without leaving the application. Future additions include RC extraction, cross-probe navigation, additional PDK support, and AI-assisted debugging. Like all Revolution EDA tools, LVS is available under the Mozilla Public License v2.0 with Commons Clause — no licensing fees or subscription requirements

Hello In cadence For tsmc65nm how to do stacking like shown in picture? Or how can we model like this ?

Hello, is it possible to run SPICE simulations on SKY130 using Synopsys HSPICE? I'm wondering if the SKY130 PDK provides HSPICE-compatible model files, or if the models only work with ngspice/Xyce. Any pointers would be appreciated. Thanks!

Ondevtra PD Lab turns OpenROAD RTL-to-GDSII into a guided desktop learning experience — helping students run real physical design labs, edit scripts, and understand each stage without setup complexity. Mac beta: https://ondevtra.com/pd-lab-download.html

How i cam reduce the poly polcontact od contact resistance for fingers 4 pmos transistor where 4 poly joined with metal and had the parallel contacts