The Strategic Evolution of VSD RISC-V/FPGA Development Boards: Why We Built What We Built The RISC-V and VLSI communities are rewriting the rules of computing, but innovation requires more than ideas—it demands tools that bridge ambition and execution. At VSD, we’ve spent three years crafting a lineage of development boards to solve critical gaps in this ecosystem. Here’s why each board exists and how they empower engineers, educators, and startups: 1. VSDSquadron Main (2023) Born from a glaring need in academia, the Main board became the first platform to merge industrial-grade VLSI workflows (RTL-to-GDSII) with hands-on RISC-V programming. With a 100MHz VexRISC-V core and 38 GPIOs, it gave students a sandbox to validate both chip design and embedded software—a rarity in curricula dominated by theory. But as RISC-V adoption grew, developers demanded affordability, not just academia-grade rigor. 2. VSDSquadron Mini (2024) The Mini answered the call for accessibility. By stripping down to essentials—24MHz core, 15 I/Os, and 10-bit ADC—we cut costs by 60%, making RISC-V development viable for hobbyists and startups. Its simplicity became its strength: a gateway for IoT prototypes and edge devices. Yet, as commercial projects scaled, the need for enterprise-grade performance became undeniable. 3. <https://www.vlsisystemdesign.com/vsdsquadronPro/?awt_a=5L_6&awt_l=Dd2JQ&awt_m=3kQG4Y9L8wA8._6|VSDSquadron PRO (2024)>* The PRO board marked our pivot to industrial adoption. With SiFive’s 320MHz FE310-G002, USB-C, and Quad-SPI Flash, it delivers the throughput and reliability needed for robotics, automation, and high-performance computing. This wasn’t just about speed—it was about aligning RISC-V with legacy ecosystems while retaining open-source flexibility. 4. VSDSquadron FPGA Mini (2025) FPGAs are the unsung heroes of VLSI validation, but proprietary toolchains and costs stifle innovation. Our FPGA Mini disrupts this with 5K LUTs, open-source workflows, and 39 configurable I/Os—a 70% cost reduction over traditional solutions. It’s not just an FPGA board; it’s a statement that ASIC prototyping should be accessible to all. We didn’t just build boards—we built stepping stones. The Main teaches, the Mini lowers barriers, the PRO competes with legacy architectures, and the FPGA Mini dismantles proprietary walls. To the Engineers and Educators Shaping Tomorrow Your feedback drove this evolution. When academia needed rigor, you spoke. When startups needed simplicity, you demanded it. Now, as RISC-V reshapes industries, we’re committed to delivering tools that keep pace with your ambition. So What’s next? WiFi/BLE, AI/ML acceleration, security co-processors, and tighter cloud integration - all guided by your needs. The future of open computing isn’t just about instruction sets; it’s about enabling your ideas without compromise.

You are either building cores or depending on those who do. The RISC-V based MYTH Workshop is where you move beyond concepts and actually build a modular, pipelined RISC-V processor from scratch. https://www.vlsisystemdesign.com/riscv-based-myth/ Instruction fetch, decode, ALU design, memory handling, control flow - every critical block, connected the way real CPUs are built. This is not a simulation exercise. This is how real engineers are made. The final cohort of the quarter closes in the next 24 hours. If you are serious about mastering processor design, now is the time to act. Learn and build here

what is the hightes voltage process we can use with FOSS tools?

Hi @jeffdi , r u accepting tapeouts? The website seems down

#C016G7Z8GDR I am working on a eComemrce project looking for python programmers. call me if you want to join : popaisle.com good luck with semicon !

Anyone know if there's a flash memory cell available?

⁦Subject: ChipFoundry: Reserve Your Shuttle for Fall & Explore ReRAM Support Hello everyone, ChipFoundry is excited to announce that reservations are now open for our upcoming shuttles in September and November! • A $500 deposit is required to secure your slot. • Universities needing to use a purchase order should contact us at info@chipfoundry.io. We encourage you to book your spots early! Make a reservation here: https://chipfoundry.io/#schedule For submission details, visit: https://chipfoundry.io/how-it-works Based on feedback from several customers, we’re also looking at Resistive Random-Access Memory (ReRAM) support for the September shuttle. If you have an interest, please drop us a message #C08RG7C0WLC or email us at info@chipfoundry.io Please contact us at info@chipfoundry.io if you have any questions or need more information. Thanks! The ChipFoundry Team⁦

13-year-old Ahtesham from Class 7 just built his own 5-stage pipelined RISC-V CPU core in a workshop meant for college students! Check his incredible story here: https://www.linkedin.com/posts/kunal-ghosh-vlsisystemdesign-com-28084836_13year-ahtesham-risc-activity-7326114041641283585-X9qs?utm_source=share&amp;utm_medium=member_desktop&amp;rcm=ACoAAAeZe4ABRnXXgcvVesykjXO-9WZxOuR05PE

The Tipping Point of Computing By 2030, RISC-V is projected to dominate 30% of the CPU market, driven by adoption from industry titans like NVIDIA, Intel, and Google. This open-source ISA isn’t just an alternative—it’s the foundation of tomorrow’s AI accelerators, IoT ecosystems, and sovereign semiconductor strategies. The message is clear: RISC-V skills are no longer optional. Why This Deadline Matters The *NASSCOM RISC-V MYTH Program*—India’s flagship initiative to democratize RISC-V expertise—closes registrations in 13 hours. Here’s why this is your last chance to act: 1. Career Survival - Engineers without RISC-V proficiency risk obsolescence as companies like Tenstorrent, Ventana, and DIR-V-backed startups prioritize hands-on expertise. Early adopters command 25–40% salary premiums, a trend accelerating with RISC-V’s market dominance. 2. Global Validation - From India’s DIR-V mission to China’s $140M RISC-V investment, nations are betting on open-source architectures to break dependency on legacy technologies. The MYTH Program aligns directly with these strategic goals, offering skills critical to national and corporate sovereignty. 3. Education Revolution - The recent recognition of the VSD RISC-V for High Schools Program on RISC-V International’s 15-year anniversary page proves that RISC-V education is scalable across age groups. MYTH builds on this success, bridging academia and industry with a curriculum validated by global leaders. What You’ll Master • RISC-V Core Design: From ISA fundamentals to synthesizable core implementation. • Verification Workflows: Debug real-world RTL designs using open-source methodologies. • Industry Alignment: Contribute to India’s DIR-V mission while preparing for global roles. Who Must Enroll • Engineers: Transition from theoretical knowledge to tape-out-ready skills. • Students: Secure internships/placements at RISC-V-driven companies. • Educators: Lead curriculum development for the semiconductor workforce of 2030. Act Now or Miss Forever With 13 hours left, delaying enrollment means surrendering your edge in a hyper-competitive market. Final Steps 1. Register Now: Secure your seat here. 2. Share Widely: Tag peers, students, or mentors who need this wake-up call. 3. Ask Questions: Comment below—I’ll answer queries on placements, projects, or RISC-V trends.

The chipathon post is live. Please share with your networks. https://www.linkedin.com/feed/update/urn:li:activity:7330999483943514112/

It's go time! The 2025 Challenge for the Makerchip ASIC Design Showdown is officially issued. Get your ships ready and gear up for Space Battle! You have all summer to design the control circuits for your fleet in this global event–the first-ever of its kind! Fun, glory, skill development, and prizes! Showdown info: https://lnkd.in/emYewchg Contest repository: https://lnkd.in/eiY_3ge9

The future of computing is open. RISC-V is no longer just an alternative - it's becoming the foundation of modern embedded systems, custom SoCs, and AI accelerators. If you're a student, engineer, or academic aiming to stay relevant in the fast-evolving semiconductor space, this is your call to action. The *RISC-V based MYTH workshop - Microprocessor for You in Thirty Hours*—is not just another course. It’s a guided journey where you start from the fundamentals of computer architecture and end up designing, simulating, and debugging your own RISC-V processor on an FPGA. Along the way, you’ll master instruction fetch, decode, execution, pipeline design, hazard resolution, and testbench development—skills that are directly aligned with what today’s top chip design teams are hiring for. This isn’t a simulation-only experience. You’ll build a real project that strengthens your technical portfolio and helps you speak the language of silicon. Whether you're aiming for roles in embedded systems, digital design, or RISC-V development, this program sets you on the right trajectory. Only five cohorts remain for 2025. Make sure you don’t miss out. Registration link - https://www.vlsisystemdesign.com/riscv-based-myth/ Build your own processor. Get ready for the future.

A new walkthrough/promo video for the Makerchip Showdown:

On June 18, 1983, Sally Ride became the first American woman in space. Her legacy is a strategic call for today’s space industry. Read more here.

Is there anyone with good knowledge in Library characterization, I need some help in augmenting the current values related to Multiple Input Switching in to CCS timing models

might be a stupid question but anyone here also using iic osic tools? saw in the github page that it has qflow but when i type qflow gui i cant open it.

Any book or tutorials which can be used for learning the Sky130 PDK or GF180mcu PDK?

India is moving from “import and integrate” to “design, characterise, and deploy.” Semiconductors are part of that story, but so are the sensors that give them purpose. To accelerate this shift, ELCIA (Electronics City Industries Association) and VSD (VLSI System Design) are launching the Sensor Characterisation Hackathon 2025. The goal is clear: push affordable sensor modules to *Technology Readiness Level 8*—and show the data that proves it. What makes this different? • Participants must log at least 24 hours of clean, time-stamped, field data—accuracy, drift, uptime—then publish everything on GitHub. • The cost cap is tight (₹8 000 total hardware), mirroring real-world constraints. • Top teams demonstrate live at IIIT Bangalore during the ELCIA Tech Summit, alongside industry veterans shaping India’s semiconductor roadmap. Whether you’re a student, a startup team, or an engineer looking for a challenge, this is a chance to convert raw readings into proof—and add a repository of reproducible results to your portfolio. Registrations open 20 June. Details here: https://elciatechsummit.in/hackathon-2025/ See you where data meets design.

Is the Matrix/element fossi-chat server down?

An 8th-grade VSD intern just built and open-sourced a single-cycle RV32IM RISC-V CPU—and brought it to life on the VSDSquadron FPGA Mini (Lattice iCE40UP5K). From RTL to real hardware using an open toolchain (Yosys → nextpnr → IceStorm). No labs full of expensive gear—just curiosity, discipline, and a clear learning path. What’s inspiring here isn’t just the result, it’s the signal: hands-on semiconductor education can be accessible, rigorous, and joyful. If a motivated school student can do this, imagine what a college cohort—or a national talent pipeline—can achieve with the same playbook. See it yourself • GitHub (source & docs): https://github.com/bytesculptor097/rv32im-single-cycle-cpu/ • Short demo video (hardware run): • Board (VSDSquadron FPGA Mini): https://www.vlsisystemdesign.com/vsdsquadronfm/ If you’re an educator, lab lead, or industry mentor, this is a ready-to-run, frugal pathway to get students building real CPUs and learning RISC-V the right way—by doing.

Hi does anyone with bare die from a chipignite or openmpw runs have any reliable method for wirebonding (gold ball or silver wedge)? we have a few bare die remaining, but have not been able to really find a reliable wirebonding solution with the equipment we have here and would like to bond and test the last few. We run into our wedge bonder causing shorts between pads, while our semi-automatic ball bonder has just been unreliable, causing a variety of issues. If anyone has tips, or a packaging house that they have used for the exact same die, it would be great to know

Azimuth in the bay area is reliably able to bond the bare die and was the quick turn provider for Efabless.

Jeff at Chip foundry could probably send you in the right direction. Yes the same Jeff. https://chipfoundry.io/

@Xiaochen Ni did You try plasma cleaning before bonding?

Hello everyone, I hope I'm in the right section. I need to understand the power consumption of one of my circuits. Apart from the fact that I don't know how to proceed, the only thing I've been able to see is the current. But this has very high instantaneous peaks (almost 4 mA), and I've noticed that it decreases significantly if I increase the rise and fall times of the clock. I'm currently using a 125MHz clock with a period of 8nS. If the rise and fall times were around 1pS, the instantaneous current could increase dramatically. I've now delayed the rise and fall times to around 100pS, and the current peaks seem to be much lower than before. I'm wondering what the real values are for a 125MHz clock. Can you help me?

You can use a measure statement like this to find the average current: .meas tran iavg_dig AVG i(Vddd)

if anybody has negative slack openlane reports uploaded in github LMK

if anybody has negative slack openlane reports uploaded in github LMK

Did ChipFoundry get the open source silicon slack?

Where might be the right place to ask question about ChipFoundry harnesses - in particular the OpenFrame harness?